Digital frequency synthesizer device and method thereof

A method, comprising:

• receiving a first plurality of clock signals comprising a first clock signal and a second clock signal, the first and second clock signal out of phase with each other;
• receiving a second plurality of clock signals comprising a third clock signal and a fourth clock signal, the third and fourth clock signals out of phase with each other;
• receiving a plurality of enable signals representing a periodic sequence of changing enable codes, the periodic sequence of changing enable codes having a first value during a first cycle, a second value during a second cycle, and a third value during a third cycle;
• combining a subset of the first plurality of clock signals according to a first logical operation to determine a fifth clock signal;
• determining a sixth clock signal based on the fifth clock signal and the plurality of enable signals;
• combining a subset of the second plurality of clock signals according to a second logical operation to determine a seventh clock signal;
• determining an eighth clock signal based on the seventh clock signal and the plurality of enable signals;
• and
• determining a ninth clock signal based on the sixth clock signal and the eighth clock signal, the ninth clock signal having a frequency based on the changing sequence of enable codes, the sequence of enable codes changing while the ninth clock signal is being provided at the frequency, the frequency based on a length of the periodic sequence of enable codes.