Fast power up comparator

A circuit comprising:

• a differential comparator having a positive output and a negative output;
• an output stage connected to the differential comparator, the output stage configured to provide a single output based on the positive output and the negative output;
• a first current source connected to the differential comparator and the output stage;
• a second current source selectively connected to the differential comparator and the output stage;
• a third current source connected to the differential comparator and the output stage;
• and
• a fourth current source selectively connected to the differential comparator and the output stage,
• wherein
• the first current source and the third current source are configured to supply power to (i) the differential comparator while the differential comparator is in a low-power state, and (ii) the output stage while the output stage is in a low-power state, and
• the second current source and the fourth current source are configured to periodically supply power (i) to transition the differential comparator from the low-power state of the differential comparator to a power-on state, and (ii) to transition the output stage from the low-power state of the output stage to a power-on state,
• wherein the differential comparator comprises
• a first differential stage including
• a first pull-down transistor having a first source-drain region, and
• a second pull-down transistor having second source-drain region, wherein the second source-drain region is connected to the first source-drain region,
• wherein the first current source is connected to the first source-drain region and the second source-drain region, and
• wherein the second current source is selectively connected to the first source-drain region and the second source-drain region, and
• a first set of switches configured to provide the selective connecting of the second current source to the first source-drain region and the second source-drain region, wherein the first set of switches is configured to receive
• a set of first control signals to periodically close the first set of switches and power on the first differential stage, and
• a set of second control signals to periodically open the first set of switches and power down the first differential stage to a low-power state,
• a second differential stage including
• a first pull-up transistor having a third source-drain region, and
• a second pull-up transistor having a fourth source-drain region, wherein the fourth source-drain region is connected to the third source-drain region,
• wherein the third current source is connected to the third source-drain region and the fourth source-drain region,
• wherein the fourth current source is selectively connected to the third source-drain region and the fourth source-drain region, and
• a second set of switches configured to provide the selective connecting of the fourth current source to the third source-drain region and the fourth source-drain region, and
• wherein the second set of switches is configured to receive
• the set of first control signals to periodically close the second set of switches and power on the second differential stage, and
• the set of second control signals to periodically open the second set of switches and power down the second differential stage to a low-power state.