Smart edge detector
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShu-Chun Yang, Jinn-Yeh Chien
Life of this patent
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Abstract
This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering.
Claims20
An edge detector comprising:
- a first device configured to receive a first clock as a first data input and a second clock as a first clock input, and provide a first device output;
- a delay element configured to receive the second clock as an input and provide a third clock delayed from the second clock;
- a second device configured to receive the first clock as a second data input and the third clock as a second clock input, and provide a second device output;
- an edge detector output configured to generate an edge detector output signal based on a logic level of the first device output and of the second device output, wherein the edge detector output signal is used to select the second clock if the second device output is at a first logic level and to select an inverse of the second clock if the second device output is at a second logic level.
An edge detector comprising:
- a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels;
- a first RC circuit configured to charge the first pulse;
- a second RC circuit configured to charge the second pulse;
- and
- a circuitry configured to receive the first clock, the circuitry is configured to provide a select signal to select an edge of the second clock for triggering based on a width of the first pulse or of the second pulse and the first clock.
A circuit comprising:
- a transmitter domain configured to receive a first clock and a first data signal and to generate a first output signal;
- a receiver domain configured to receive the first clock, a second clock and the first output signal and to generate a second output signal, the receiver domain including an edge detector comprising:
- a pulse generator configured to generate a first pulse when the first clock and the second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels;
- a first RC circuit configured to charge the first pulse;
- a second RC circuit configured to charge the second pulse;
- and
- a circuitry configured to receive the first clock, and to provide a select signal to select an edge of the second clock for triggering based on a width of the first pulse or of the second pulse and the first clock.
Dependencies are inferred from the claim text.