Method of operating phase-lock assistant circuitry
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Chang Lin, Chan-Hong Chern, Steven Swei, Ming-Chieh Huang, Tien-Chun Yang
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Abstract
A method of operating a charge pump of a phase-lock assistant circuit includes determining a first relative timing relationship of a phase of a data signal to a phase of a first phase clock. A second relative timing relationship of the phase of the data signal to a phase of a second phase clock is determined, and the first and second phase clocks have a 45° phase difference. An up signal and a down signal are generated in response to the first relative timing relationship and the second relative timing relationship. The charge pump circuit is driven according to the up signal and the down signal.
Claims20
A method of operating a charge pump of a phase-lock assistant circuit, the method comprising:
- determining a first relative timing relationship of a phase of a data signal during a current clock cycle to a phase of a first phase clock during the current clock cycle;
- determining a second relative timing relationship of the phase of the data signal during the current clock cycle to a phase of a second phase clock during the current clock cycle, the first and second phase clocks having a 45° phase difference;
- generating an up signal and a down signal in response to the first relative timing relationship, and the second relative timing relationship, a third relative timing relationship of a phase of the data signal during a previous clock cycle to a phase of the first phase clock during the previous clock cycle, and a fourth relative timing relationship of the phase of the data signal during the previous clock cycle to a phase of the second phase clock during the previous clock cycle;
- and
- driving the charge pump circuit according to the up signal and the down signal.
A method of operating a charge pump of a phase-lock assistant circuit, the method comprising:
- setting an up signal to a high logic value if a previous relative timing relationship indicates that a rising edge of a data signal during a previous clock cycle falls within phase 225° to 270° of a first phase clock and a current relative timing relationship indicates that a rising edge of the data signal during a current clock cycle falls within phase 180° to 225° of the first phase clock;
- setting the up signal to a low logic value if the previous relative timing relationship indicates that the rising edge of the data signal during the previous clock cycle falls within phase 135° to 180° of the first phase clock and the current relative timing relationship indicates that the rising edge of the data signal during the current clock cycle falls within phase 90° to 135° of the first phase clock;
- setting a down signal to the high logic value if the previous relative timing relationship indicates that the rising edge of the data signal during the previous clock cycle falls within phase 90° to 135° of the first phase clock and the current relative timing relationship indicates that the rising edge of the data signal during the current clock cycle falls within phase 135° to 180° of the first phase clock;
- setting the down signal to the low logic value if the previous relative timing relationship indicates that the rising edge of the data signal during the previous clock cycle falls within phase 180° to 225° of the first phase clock and the current relative timing relationship indicates that the rising edge of the data signal during the current clock cycle falls within phase 225° to 270° of the first phase clock;
- and
- driving the charge pump circuit according to the up signal and the down signal.
A method comprising:
- receiving, by a first circuit, an input signal, a first phase clock, a second phase clock, and a third phase clock;
- generating, by the first circuit, a first early signal and a first late signal in response to the input signal, the first phase clock, the second phase clock, and the third phase clock;
- receiving, by a second circuit, the input signal, a fourth phase clock, a fifth phase clock, and a sixth phase clock;
- and
- generating, by the second circuit, a second early signal and a second late signal in response to the input signal, the fourth phase clock, the fifth phase clock, and the sixth phase clock, wherein
- the first phase clock and the fourth phase clock has a 45° phase difference;
- the second phase clock has a 180° phase compared with the first phase clock;
- the third phase clock has a 90° phase compared with the first phase clock;
- the fourth phase clock has a 45° phase compared with the first phase clock;
- the fifth phase clock has a 225° phase compared with the first phase clock;
- and
- the sixth phase clock has a 135° phase compared with the first phase clock.
Dependencies are inferred from the claim text.