Internal clock gating apparatus

A system comprising:

• an internal clock gating apparatus comprising:
• a static logic block configured to receive a clock signal and a clock enable signal;
• and
• a domino logic block configured to receive the clock signal and a control signal from an output of the static logic block, wherein:
• an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state, and
• the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state;
• and
• a plurality of circuits having a clock input coupled to an output of the internal clock gating apparatus.

A circuit comprising:

• a static logic block configured to receive a clock signal and a clock enable signal;
• and
• a domino logic block configured to receive the clock signal and a control signal from an output of the static logic block, wherein
• an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state, and
• the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state.