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US 8,575,963 B2Granted
Buffer system having reduced threshold current
AssigneeFairchild Semiconductor Corporation
InventorTyler Daigle
Life of this patent
Estimating the term…
Abstract
A buffer system is provided that reduces threshold current using a current source to provide power to one or more stages of the buffer system. The buffer system may also include delay management techniques that balances all of, or part of, a delay that may be imparted to an input signal by the current source. In addition, hysteresis techniques may be used to provide enhanced noise management of the input signal.
Claims11
An input buffer system, comprising:
- first inverter stage circuitry configured to invert an input digital signal that switches between states;
- and
- first current source circuitry comprising a first current source coupled between a first voltage rail and the first inverter stage circuitry, the first current source is configured to generate a first reference current to supply power to the first inverter stage circuitry, the first current source circuitry is further configured to limit a threshold current of the first inverter stage circuitry, wherein the first reference current limits a switching speed of the first inverter stage circuitry to a first switching speed;
- first enable/disable circuitry configured to provide a bypass path from the first voltage rail to the first inverter stage circuitry, wherein the bypass path bypasses the first current source circuitry;
- and wherein the first voltage rail provides a second reference current to supply power to the first inverter stage circuitry;
- wherein the first inverter stage circuitry switches at a second switching speed when powered by the second reference current;
- and wherein the second reference current is greater than the first reference current and wherein the second switching speed is greater than the first switching speed;
- second inverter stage circuitry coupled together in series with the first inverter stage circuitry, the second inverter stage circuitry is configured to invert an output of the first inverter stage circuitry;
- second current source circuitry coupled between the first voltage rail and the second inverter stage circuitry and configured to generate a third reference current to supply power to the second inverter stage circuitry, the second current source is further configured to limit a threshold current of the second inverter stage circuitry;
- wherein the third reference current limits a switching speed of the second inverter stage circuitry to a third switching speed;
- and
- second enable/disable circuitry configured to provide a bypass path from the first voltage rail to the second inverter stage circuitry, wherein the bypass path bypasses the second current source circuitry;
- and wherein the first voltage rail provides a fourth reference current to supply power to the second inverter stage circuitry;
- wherein the second inverter stage circuitry switches at a fourth switching speed when powered by the fourth reference current;
- and wherein the fourth reference current is greater than the third reference current and wherein the fourth switching speed is greater than the third switching speed.
12 more elements
A system, comprising:
- first inverter stage circuitry configured to invert an input digital signal that switches between states;
- first current source circuitry comprising a first current source coupled between a first voltage rail and the first inverter stage circuitry, the first current source is configured generate a first reference current to supply power to the first inverter stage circuitry, the first current source circuitry is further configured to limit a threshold current of the first inverter stage circuitry, wherein the first reference current limits a switching speed of the first inverter stage circuitry to a first switching speed;
- and
- first enable/disable circuitry configured to provide a bypass path from the first voltage rail to the first inverter stage circuitry, wherein the bypass path bypasses the first current source circuitry;
- and wherein the first voltage rail provides a second reference current to supply power to the first inverter stage circuitry;
- wherein the first inverter stage circuitry switches at a second switching speed when powered by the second reference current;
- and wherein the second reference current is greater than the first reference current and wherein the second switching speed is greater than the first switching speed;
- and
- second inverter stage circuitry coupled together in series with the first inverter stage circuitry, the second inverter stage circuitry is configured to invert an output of the first inverter stage circuitry;
- and
- second current source circuitry coupled between the first voltage rail and the second inverter stage circuitry and configured to generate a third reference current to supply power to the second inverter stage circuitry, the second current source circuitry is further configured to limit a threshold current of the second inverter stage circuitry;
- wherein the third reference current limits a switching speed of the second inverter stage circuitry to a third switching speed;
- and
- second enable/disable circuitry configured to provide a bypass path from the first voltage rail to the second inverter stage circuitry, wherein the bypass path bypasses the second current source circuitry;
- and wherein the first voltage rail provides a fourth reference current to supply power to the second inverter stage circuitry;
- wherein the second inverter stage circuitry switches at a fourth switching speed when powered by the fourth reference current;
- and wherein the fourth reference current is greater than the third reference current and wherein the fourth switching speed is greater than the third switching speed;
- and
- hysteresis circuitry, coupled to the first inverter stage circuitry, configured to control a switch transition threshold of the input digital signal by the first inverter stage circuitry so that the Low to High switch transition threshold is greater than a High to Low switch transition threshold.
16 more elements
A method comprising:
- providing a first reference current to supply power to a first inverter stage circuitry, the first reference current source is configured to limit a threshold current of the first inverter stage circuitry, wherein the first reference current limits a switching speed of the first inverter stage circuitry to a first switching speed;
- providing first enable/disable circuitry configured to bypass the first reference current and couple the first inverter stage circuitry to a first voltage rail, wherein the first voltage rail provides a second reference current to supply power to the first inverter stage circuitry;
- wherein the first inverter stage circuitry switches at a second switching speed when powered by the second reference current;
- and wherein the second reference current is greater than the first reference current and wherein the second switching speed is greater than the first switching speed;
- providing a second inverter stage circuitry coupled in series with the first inverter stage circuitry;
- wherein second inverter stage circuitry is configured to invert the output of the first inverter stage circuitry;
- providing a third reference current to supply power to the second inverter stage circuitry, the third reference current source is configured to limit a threshold current of the second inverter stage circuitry, wherein the third reference current limits a switching speed of the second inverter stage circuitry to a third switching speed;
- and
- providing second enable/disable circuitry configured to bypass the third reference current and couple the second inverter stage circuitry to a first voltage rail, wherein the first voltage rail provides a fourth reference current to supply power to the second inverter stage circuitry;
- wherein the second inverter stage circuitry switches at a fourth speed when powered by the fourth reference current;
- and wherein the fourth reference current is greater than the third reference current and wherein the fourth switching speed is greater than the third switching speed.
8 more elements
Dependencies are inferred from the claim text.