Multi-valued driver circuit
AssigneeAdvantest Corporation
InventorShoji Kojima
Life of this patent
Estimating the term…
Abstract
A multi-valued driver circuit selectively outputs, to a transmission line, one from among multiple voltages according to a selection signal. A memory circuit stores setting data which define the respective levels of the multiple voltages. According to the selection signal, a selector circuit selects one from among the multiple setting data stored in the memory circuit. A Thevenin termination circuit outputs a voltage that corresponds to the upper M bits of the data thus selected by the selector circuit. An R-2R ladder circuit outputs a voltage that corresponds to the lower Nl bits of the data thus selected by the selector circuit.
Claims12
A multi-valued driver circuit configured to selectively output, to a transmission line, one from among K voltages according to a selection signal, K representing an integer of 2 or more, and to be capable of independently adjusting the K voltages according to (M+Nl)-bit setting data, M and Nl each representing an integer, the multi-valued driver circuit comprising:
- an output port connected to the transmission line;
- first memory configured to store the upper M bits of the setting data for each of the K voltages;
- second memory configured to store the lower Nl bits of the setting data for each of the K voltages;
- M first selectors respectively provided for the upper M bits of the setting data, each configured to receive the corresponding bits of the K setting data, and to select one from among the corresponding bits of the K setting data according to the selection signal;
- Nl second selectors respectively provided for the lower Nl bits of the setting data, each configured to receive the corresponding bits of the K setting data, and to select one from among the corresponding bits of the K setting data according to the selection signal;
- M first buffer units respectively provided for the M first selectors, and each configured to output a voltage that corresponds to the output value of the corresponding first selector;
- M first resistors respectively provided for the M first buffer units, each configured to have a resistance value R, and each arranged such that the output voltage of the corresponding first buffer unit is applied to one terminal thereof, and the other terminal thereof is connected to the output port;
- Nl second buffer units respectively provided for the Nl second selectors, and each configured to output a voltage that corresponds to the output value of the corresponding second selector;
- a third buffer unit configured to generate a fixed voltage;
- Nl second resistors respectively provided for the Nl second buffer units, each configured to have a resistance value R, and each arranged such that the output voltage of the corresponding second buffer unit is applied to one terminal thereof;
- a third resistor configured to have a resistance value R, and arranged such that the output voltage of the third buffer unit is applied to one terminal thereof;
- and
- Nl fourth resistors connected so as to form a R-2R ladder network together with the Nl second resistors and the third resistor, with the aforementioned output port as an output terminal of the R-2R ladder network.
A multi-valued driver circuit configured to selectively output, to a transmission line, one from among K voltages according to a selection signal, where K represents an integer of 2 or more, and to be capable of independently adjusting the K voltages according to (Nu+Nl)-bit setting data, where Nu and Nl each represent an integer, the multi-valued driver circuit comprising:
- an output port connected to the transmission line;
- first memory configured to store the upper Nu bits of the setting data for each of the K voltages;
- second memory configured to store the lower Nl bits of the setting data for each of the K voltages;
- Nu first selectors respectively provided for the upper Nu bits of the setting data, and each configured to receive the corresponding bits of the K setting data, and to select one from among the corresponding bits of the K setting data according to the selection signal;
- Nl second selectors respectively provided for the lower Nl bits of the setting data, and each configured to receive the corresponding bits of the K setting data, and to select one from among the corresponding bits of the K setting data according to the selection signal;
- L (L=2Nu−1) first buffer units grouped into a plurality of groups, the j-th (j=0, 1, . . . , Nu−1) group including 2j first buffer units, and arranged such that the input terminals of the first buffer units that belong to the same group are connected together for each group, and such that the 2j first buffer units that belong to the j-th group each output a voltage that corresponds to the output value of the first selector that corresponds to the lower (j+Nl)-th bit of the setting data;
- L first resistors respectively provided for the L first buffer units, each configured to have a resistance value R, and each arranged such that the output voltage of the corresponding first buffer unit is applied to one terminal thereof and the other terminal thereof is connected to the output port;
- Nl second buffer units respectively provided for the Nl second selectors, and each configured to output a voltage that corresponds to the output value of the corresponding second selector;
- Nl second resistors respectively provided for the Nl second buffer units, each configured to have a resistance value R, and each arranged such that the output voltage of the corresponding second buffer unit is applied to one terminal thereof;
- a third buffer unit configured to generate a fixed voltage;
- and
- Nl fourth resistors each configured to have a resistance value of R/2, and connected so as to form a R-2R ladder network together with the Nl second resistors and the third resistor, with the aforementioned output port as an output terminal of the R-2R ladder network.
Dependencies are inferred from the claim text.