Programmable on-chip logic analyzer apparatus, systems, and methods

An apparatus comprising:

• an input signal selection macro module (ISSMM) stage including circuitry to perform at least one of selecting a subset of signals from a device under test or introducing at least one differential delay between ones of the subset of signals;
• a programmable logic macro module (PLMM) stage including circuitry to perform a set of selectable logic functions on the subset of signals;
• an event function result output to indicate that the subset of signals as acted upon by the ISSMM stage has transitioned to a watched-for state as identified by a configuration programmed into the PLMM stage;
• first and second pluralities of input signal selection macro module (ISSMMs), each of the first plurality of ISSMMs including circuitry to select a first initial input signal from a set of input signals on a set of input signal paths and each of the second plurality of ISSMMs including circuitry to select a second initial input signal from the set of input signals on the set of input signal paths;
• a first PLMM coupled to the first plurality of ISSMMs, the first PLMM including circuitry to perform a first selectable logic function on at least one of the first initial input signals to yield a first intermediate result;
• a second PLMM coupled to the second plurality of ISSMMs, the second PLMM including circuitry to perform a second selectable logic function on at least one of the second initial input signals to yield a second intermediate result;
• a third PLMM coupled to the first and second PLMMs, the third PLMM including circuitry to perform a third selectable logic function on at least one of the first or second intermediate results to yield a third intermediate result;
• and
• a fourth PLMM coupled to the third PLMM, the fourth PLMM including circuitry to perform a fourth selectable logic function on at least one of the third intermediate result or on at least one of the second initial input signals to yield an event function result.

A method comprising:

• selecting a first plurality of initial input signals from a set of input signals on a set of input signal paths using a first plurality of input signal selection macro modules;
• selecting a second plurality of initial input signals from the set of input signals on the set of input signal paths using a second plurality of input signal selection macro modules;
• performing a first selectable logic function on at least one of the first plurality of initial input signals using a first programmable logic module to yield a first intermediate result, the first programmable logic module including first inputs to receive the at least one of the first plurality of initial input signals;
• performing a second selectable logic function on at least one of the second plurality of initial input signals using a second programmable logic macro module to yield a second intermediate result, the second programmable logic macro module including second inputs to receive the at least one of the second plurality of initial input signals, wherein the first inputs are uncoupled to the second inputs;
• performing a third selectable logic function on at least one of the first or second intermediate results using a third programmable logic macro module to yield a third intermediate result;
• and
• performing a fourth selectable logic function on at least one of (a) the third intermediate result or (b) at least one of the second plurality of initial input signals to yield an event function result.

A method comprising:

• selecting a first plurality of initial input signals from a set of input signals on a set of input signal paths using a first plurality of input signal selection macro modules;
• selecting a second plurality of initial input signals from the set of input signals on the set of input signal paths using a second plurality of input signal selection macro modules;
• performing a first selectable logic function on at least one of the first plurality of initial input signals using a first programmable logic module to yield a first intermediate result,
• performing a second selectable logic function on at least one of the second plurality of initial input signals using a second programmable logic marco module to yield a second intermediate result;
• performing a third selectable logic function on at least one of the first or second intermediate results usin a third programmable logic macro module to yield a third intermediate result;
• and
• performing a fourth selectable to logic function on at least one of (a) the third intermediate result or (b) at least one of the second plurality of initial input signals to yield an event function result
• disabling at least one of the second plurality of initial input signals at the fourth selectable logic function;
• and
• passing the third intermediate result through the fourth selectable logic function to yield the event function result, wherein the event function result is of the form (a fn1 b) fn3 (c fn2 d).

A method comprising:

• selecting a first plurality of initial input signals from a set of input signals on a set of input signal paths using a first plurality of input signal selection macro modules;
• selecting a second plurality of initial input signals from the set of input signals on the set of input signal paths using a second plurality of input signal selection macro modules;
• performing a first selectable logic function on at least one of the first plurality of initial input signals using a first programmable logic module to yield a first intermediate result,
• performing a second selectable logic function on at least one of the second plurality of initial input signals using a second programmable logic macro module to yield a second intermediate result;
• performing a third selectable logic function on at least one of the first or second intermediate results usin a third programmable logic macro module to yield a third intermediate result;
• and
• performing a fourth selectable to logic function on at least one of a the third intermediate result or (b) at least one of the second plurality of initial input signals to yield an event function result
• disabling at least one of the second plurality of initial input signals at an input of the second selectable logic function;
• and
• passing non-disabled ones of the second plurality of initial input signals through the second selectable logic function to produce an event function of the form ((a fn1 b) f3 c) f4 d.