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US 8,575,957 B2Granted
Multiple data rate interface architecture
AssigneeAltera Corporation
InventorsPhilip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
Life of this patent
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Abstract
Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
Claims18
An integrated circuit comprising:
- a first frequency divider for receiving a system clock;
- a variable delay block, coupled to the first frequency divider, for:
- generating a first delayed clock based on an output received from the first frequency divider, and outputting the first delayed clock to a phase detector;
- the phase detector, coupled to the variable delay block, for determining a relationship between the system clock and the first delayed clock;
- a second frequency divider for:
- receiving as an input the system clock;
- and
- outputting a frequency divided system clock to an up/down counter;
- and
- the up/down counter coupled to the phase detector, wherein:
- the up/down counter provides a control signal to the variable delay block;
- and
- the generation of the first delayed clock is based on the control signal.
10 more elements
A method for generating a phase control signal, the method comprising:
- receiving a system clock;
- generating, using a first frequency divider, a first frequency divided system clock;
- generating, using a variable delay block, a first delayed system clock based on the first frequency divided system clock, wherein the variable delay block outputs the first delayed clock to a phase detector;
- determining, using the phase detector, a relationship between the system clock and the first delayed system clock;
- generating, using a second frequency divider, a second frequency divided system clock;
- controlling, using an up/down counter, the generation of the first delayed system clock based on the determined relationship and the second frequency divided system clock;
- and
- outputting the phase control signal based on the first delayed system clock.
5 more elements
An integrated circuit comprising:
- a variable delay block for:
- receiving a system clock;
- generating a first delayed clock based on the received system clock;
- and
- outputting the first delayed clock to a phase detector;
- the phase detector for determining a relationship between the system clock and the first delayed clock, wherein the phase detector is coupled to the variable delay block;
- a register for:
- receiving an output of the phase detector as a first input;
- and
- outputting an up/down signal to the up/down counter;
- a frequency divider for:
- receiving as an input the system clock;
- and
- outputting a frequency divided system clock to an up/down counter;
- and
- the up/down counter coupled to the phase detector, wherein:
- the up/down counter provides a control signal to the variable delay block;
- and
- the generation of the first delayed clock is based on the control signal.
16 more elements
Dependencies are inferred from the claim text.