Structures and processes for fabrication of probe card assemblies with multi-layer interconnect

A process, comprising the steps of:

• providing a design layout for a semiconductor wafer comprising an array of semiconductor devices, wherein each of the semiconductor devices comprises a plurality of electrical connection terminals;
• providing a design for a probe chip substrate having a probe side and a contact side and comprising an array of electrically conductive substrate through-vias;
• establishing a layout for a plurality of spring contacts on the probe side of the substrate arranged to provide electrical connections to at least one of the devices and one or more electrically conductive routing layers connecting the plurality of spring contacts to a corresponding plurality of the substrate through-vias to form a set of standard electrical connections for the at least one device;
• repeating the set of standard electrical connections to provide a layout for simultaneous electrical connections from the through-vias to more than one element of the array of semiconductor devices;
• and
• establishing a layout for one or more electrically conductive routing layers on the contact side of the substrate connecting each member of the plurality of through-vias corresponding to each set of standard connections to a corresponding set contact pads on a regular grid having a pre-determined via pitch thereby establishing simultaneous electrical connections from the contact pads to one or more of the semiconductor devices.

A process, comprising the steps of:

• providing a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads;
• providing a layout of probe chip substrate having a probe side and a contact side, and through-vias at undetermined locations;
• creating a unit standard cell on the probe side of the probe chip, comprising substrate spring contacts located for contacting the connection pads on the integrated circuits and one or more electrically conductive routing layers for connecting the spring contacts to a set of probe chip substrate through vias located in a standard pattern;
• creating a wafer scale standard cell layout on the probe side of the probe chip, by stepping and repeating the standard cell layout, so that each unit cell matches a pre-selected location of an integrated circuit on the semiconductor wafer;
• providing a layout of a central structure, comprising a fixed array of vias with fixed X, Y, and Z locations;
• and
• creating auto-routed electrically conductive routing layers on the contact side of the probe chip substrate to provide electrical connections between the substrate through vias and the Z-block through vias.

A system for providing a design for a probe chip contactor for providing electrical connections between a semiconductor wafer comprising an array of semiconductor devices, and a central structure, wherein each of the semiconductor devices comprises a plurality of electrical connection terminals, the central structure having a first and a second side and an array of contact pads electrically connected to central structure through-vias on a regular grid having a pre-determined pitch extending over the usable area of the central structure, the system comprising:

• means for receiving a design for the semiconductor wafer;
• means for establishing a probe side design for a probe chip contactor;
• receiving a signal at a computer system, the signal comprising as inputs the layout of the through-vias of the probe chip contactor, and the standard layout of a central structure having a standard layout with X-Y offsets of solder pads;
• determining a routing pattern through one or more conductive layers on the connector side of the probe chip substrate to solder pads that are alignably connectable to the central structure, wherein the routing pattern is a repeated standard cell.

A process, comprising the steps of:

• providing a probe chip contactor substrate having a probe side and a contact side, and through-vias at predetermined locations;
• providing a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads;
• creating a unit standard cell on the probe side of the probe chip, comprising substrate spring contacts located for contacting the connection pads on the integrated circuits and interconnect traces for connecting the spring contacts to a set of probe chip contactor vias;
• creating a wafer scale standard cell layout on the probe side of the probe chip, by stepping and repeating the standard cell layout, so that each unit cell matches a pre-selected location of an integrated circuit on the semiconductor wafer;
• providing a layout of a central structure, comprising a fixed array of vias with fixed X, Y, and Z locations;
• and
• creating auto-routed interconnect traces in the contact side of the probe chip substrate to provide electrical connections between the substrate through vias and the Z-block through vias.

An apparatus for providing electrical connections between a semiconductor wafer comprising an array of semiconductor devices, and a central structure, wherein each of the semiconductor devices comprises a plurality of electrical connection terminals, the central structure having a first and a second side and an array of contact pads electrically connected to central structure through-vias on a regular grid having a pre-determined pitch extending over the usable area of the central structure, the apparatus comprising:

• a probe chip substrate having a usable substrate area, a probe side and a contact side opposite the probe side, and comprising an array of electrically conductive substrate through-vias and;
• a plurality of spring contacts on the probe side of the substrate arranged to provide electrical connections to at least one of the devices and one or more electrically conductive routing layers connecting the plurality of spring contacts to a corresponding plurality of the substrate through-vias to form a standard pattern of standard electrical connections for the at least one device;
• and
• a plurality of electrically conductive routing layers on the contact side of the substrate configured to electrically connect each member of the plurality of substrate through-vias corresponding to each set of standard connections to a corresponding set of contact pads on the central structure to provide simultaneous electrical connections from the central structure contact pads over the usable area of the central structure to one or more of the semiconductor device;
• wherein the routing for the plurality of electrically conductive routing layers insures full utilization of the z-block pads below each standard pattern.