Single-cycle charge regulator for digital control

A method for controlling a voltage regulator having an output configured to provide an output voltage, the method comprising:

• regulating a steady-state behavior of the output voltage, according at least to a first control value derived from a value of the output voltage and a reference value;
• correcting the output voltage responsive to a transient deviation of the output voltage, according at least to a second control value derived from the value of the output voltage, the reference value, and a gain of the voltage regulator;
• and
• adjusting a charge at the output of the voltage regulator during a present cycle subsequent to a preceding cycle during which said correcting is performed, responsive to the transient deviation of the output voltage, wherein said adjusting is performed based on a third control value derived at least from:
• a value of the first control value during the present cycle;
• a value of the first control value during the preceding cycle;
• and
• a value of the second control value during the preceding cycle.

A method for regulating a system output, the method comprising:

• controlling a first output state variable of the system output according to an error signal derived from the first output state variable and a reference signal, to keep the first output state variable in a desired steady-state;
• in response to the first output state variable deviating from the desired steady-state due to a transient event on the system output, adjusting the first output state variable during a present clock cycle to return the first output state variable to the desired steady-state, comprising:
• perturbing a second output state variable affected by the first output state variable, resulting in the second output state variable deviating from an original state to a perturbed state different from the original state by more than a specified percentage of the original state;
• and
• adjusting the second output state variable during a next clock cycle immediately following the present clock cycle, to move the second output state variable from its perturbed state towards a state that is within at least the specific percentage of its original state, while keeping the first output state variable within at least a specific percentage of the desired steady-state.

A system comprising:

• a processor;
• a memory element configured to store programming instructions executable during a present clock cycle by the processor, to:
• generate an error value based on a reference value and an output value corresponding to an output voltage of a power converter;
• calculate a steady-state control value from the error value;
• calculate a transient control value from the error value and a gain value corresponding to a gain of the power converter;
• calculate a target control value from:
• the steady-state control value;
• the transient control value;
• and
• the steady-state control value calculated during a preceding clock cycle, the transient control value calculated during the preceding clock cycle, and the target control value calculated during the preceding clock cycle;
• and
• control circuitry configured to generate a control signal according to the target control value, and regulate the output voltage of the power converter using the control signal.

A system comprising:

• first control circuitry configured to generate an error signal from:
• a reference voltage;
• and
• an output voltage appearing at an output of a power converter;
• second control circuitry configured to regulate steady-state behavior of the output voltage, according to a first control value determined based on the error signal;
• third control circuitry configured to adjust the output voltage in response to a transient event on the output voltage, according to a second control value determined based on the error signal and a gain of the power converter;
• fourth control circuitry configured to adjust a charge at the output of the power converter responsive to the transient event and during a clock cycle subsequent to a preceding clock cycle during which the output voltage is adjusted in response to the transient event, and wherein the fourth control circuitry is configured to adjust the charge according to a third control value determined based at least on:
• the first control value from the clock cycle subsequent to the preceding clock cycle;
• the second control value from the preceding clock cycle;
• and
• the third control value from the preceding clock cycle.