Semiconductor device and method of manufacturing the same

A device comprising:

• a first semiconductor chip including a first main surface and a second main surface opposite to the first main surface, the first semiconductor chip further including a plurality of chip electrodes on a side of the first main surface;
• a first seal including a third main surface and a fourth main surface opposite to the third main surface, the first seal including a hole formed therein and being substantially the same in thickness as the first semiconductor chip to accommodate the first semiconductor chip in the hole such that the third main surface of the first seal is substantially coplanar with the first main surface of the first semiconductor chip and the fourth main surface of the first seal is substantially coplanar with the second main surface of the first semiconductor chip;
• an insulating layer formed in contact with the first main surface of the first semiconductor chip and with the third main surface of the first seal, the insulating layer including
• a plurality of holes that expose the chip electrodes of the first semiconductor chip, respectively;
• a plurality of ball electrodes formed over the insulating layer apart from the chip electrodes;
• a plurality of rewiring layers each formed on the insulating layer to interconnect an associated one of the chip electrodes to a corresponding one of the ball electrodes;
• a second semiconductor chip stacked over the second surface of the first semiconductor chip;
• and
• a second seal that seals at least a first gap between the first and second semiconductor chips.

A device comprising:

• a first semiconductor chip including a first main surface and a second main surface opposite to the first main surface, the first semiconductor chip further including a plurality of chip electrodes on a side of the first main surface;
• a first seal including a third main surface and a fourth main surface opposite to the third main surface, the first seal including a hole formed therein and being substantially the same in thickness as the first semiconductor chip to accommodate the first semiconductor chip in the hole such that the third main surface of the first seal is substantially coplanar with the first main surface of the first semiconductor chip and the fourth main surface of the first seal is substantially coplanar with the second main surface of the first semiconductor chip;
• an insulating layer formed in contact with the first main surface of the first semiconductor chip and with the third main surface of the first seal, the insulating layer including a plurality of holes that expose the chip electrodes of the first semiconductor chip, respectively;
• a plurality of ball electrodes formed over the insulating layer apart from the chip electrodes;
• a plurality of rewiring layers each formed on the insulating layer to interconnect an associated one of the chip electrodes to a corresponding one of the ball electrodes;
• and
• a chip stacked structure including a plurality of second semiconductor chips that are stacked on one another, the chip stacked structure including a plurality of bump electrodes on a lowermost one of the second semiconductor chips, and the chip stacked structure stacked over the second main surface of the first semiconductor chip, the bump electrodes being electrically connected to the chip electrodes of the first semiconductor chip.

A device comprising:

• a first semiconductor chip including a first surface, a second surface opposite to the first surface, side surfaces joined to the first and second surfaces to define edges thereof, and a plurality of first electrodes formed on the second surface;
• a first sealing resin surrounding the side surfaces of the first semiconductor chip, the first sealing resin being in direct contact with the side surfaces of the first semiconductor chip and including a lower surface which is substantially coplanar with the second surface of the first semiconductor chip, the lower surface of the first sealing resin including a plurality of portions;
• an insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first sealing resin, the insulating layer including a plurality of holes that expose the first electrodes of the first semiconductor chip, respectively;
• a plurality of ball electrodes formed over the insulating layer apart from the first semiconductor chip, each of the ball electrodes being vertically aligned with an associated one of the portions of the lower surface of the first sealing resin;
• and
• a plurality of rewiring layers each connected to an associated one of the first electrodes through an associated one of the holes of the insulating layer and elongated over the insulating layer to reach a corresponding one of the ball electrodes;
• wherein the first semiconductor chip includes a plurality of second electrodes formed on the first surface, the plurality of second electrodes are electrically connected to the plurality of first electrodes, respectively.