Wafer-level packaging with compression-controlled seal ring bonding
AssigneeSandia Corporation
InventorAnthony J. Farino
Life of this patent
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Abstract
A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.
Claims26
A method of providing a device in a sealed package, comprising:
- aligning a first continuous seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a second continuous seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains a device to be packaged;
- forcibly effecting movement of the first and second wafer surfaces toward one another with the first and second seal rings aligned in opposing relationship and thereby compressing the first and second seal rings against one another;
- and
- providing between the first and second wafer surfaces a physical barrier, other than the first and second seal rings, against said movement.
A method of preparing a semiconductor wafer for use in packaging a device in a sealed package, comprising:
- providing on a surface of said wafer a continuous seal ring having a bonding surface generally parallel to and offset from said wafer surface, said bonding surface adapted to contact a cooperating continuous seal ring on another semiconductor wafer during a seal ring bonding operation;
- and
- providing on said wafer, with said seal ring interposed therebetween, first and second stop surfaces generally parallel to said bonding surface and disposed between said bonding surface and said wafer surface, said first and second stop surfaces respectively adapted to contact cooperating stop surfaces on said another wafer while said bonding surface is contacting said another seal ring during said seal ring bonding operation.
A wafer assembly for use in packaging a device in a sealed package, comprising:
- a semiconductor wafer;
- a continuous seal ring provided on a surface of said wafer and having a bonding surface generally parallel to and offset from said wafer surface, said bonding surface adapted to contact a cooperating continuous seal ring on another semiconductor wafer during a seal ring bonding operation;
- and
- means defining first and second stop surfaces generally parallel to said bonding surface and disposed between said bonding surface and said wafer surface, said first and second stop surfaces adapted to contact cooperating stop surfaces on said another wafer while said bonding surface is contacting said another seal ring during said seal ring bonding operation, wherein said seal ring is interposed between said first and second stop surfaces.
A sealed device package assembly, comprising:
- a device provided on a first wafer portion of a first semiconductor wafer and interposed between said first wafer portion and a second wafer portion of a second semiconductor wafer;
- a first seal formed between said first and second wafer portions and surrounding a part of said first wafer portion that contains said device;
- and
- a further seal formed between said first and second wafer portions and surrounding said part of said first wafer portion, wherein:
- said first seal and said further seal are compressively formed seals and the first seal is a product of more compression than the further seal.
Dependencies are inferred from the claim text.