US 8,575,742 B1Granted

Semiconductor device with increased I/O leadframe including power bars

AssigneeAmkor Technology, Inc.

InventorsWan Jong Kim, Young Tak Do, Byong Woo Cho

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Abstract

A semiconductor device or semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package, and further to provide one or more power bars in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die paddle or die pad defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the power bars, leads, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and some of the leads being exposed in a common exterior surface of the package body. The bottom surface(s) of the power bar(s) may also be exposed in such common exterior surface of the package body, or the power bar(s) may be completely covered by the package body.

Claims19

Dependent claims

A semiconductor package, comprising:

a generally planar die pad defining multiple peripheral edge segments;
a plurality of power bars arranged to at least partially circumvent the die pad in spaced relation thereto;
a plurality of first leads disposed in spaced relation to the power bars and the die pad, the first leads being positioned inwardly of the power bars between the power bars and the die pad, with at least some of the first leads being electrically isolated from the die pad;
a plurality of second leads disposed in spaced relation to and positioned outwardly of the power bars, each of the second leads including first and second downsets formed therein in spaced relation to each other;
a plurality of third leads disposed in spaced relation to and positioned outwardly of the power bars, at least some of the third leads including a downset formed therein;
a semiconductor die attached to the die pad and electrically connected to at least one of each of the first, second and third leads, and to at least one of the power bars;
and
a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads, the power bars, and the semiconductor die such that the first and second downsets of the second leads and the downsets of the third leads are covered by the package body, at least portions of the die pad, the first leads and the second leads are exposed in and substantially coplanar with the bottom surface of the package body, and portions of the third leads protrude from at least one of the side surfaces of the package body.

5 more elements

A semiconductor package, comprising:

a die pad;
a power bar arranged in spaced relation with and generally parallel to a peripheral edge segment of the die pad;
a plurality of first leads disposed in spaced relation to the power bar and the die pad, the first leads being positioned generally perpendicularly inward of the power bar between the power bar and the die pad, with at least some of the first leads being electrically isolated from the die pad;
a plurality of second leads disposed in spaced relation to and positioned generally perpendicularly outward of the power bar;
a plurality of third leads disposed in spaced relation to and positioned outwardly of the power bar;
a semiconductor die attached to the die pad and electrically connected to at least one of each of the first, second and third leads, and to the power bar;
and
a package body defining a generally planar bottom surface and multiple side surfaces, the package body at least partially encapsulating the first, second and third leads, the power bar, and the semiconductor die such that at least portions of the die pad, the first leads and the second leads are exposed in and substantially coplanar with the bottom surface of the package body, and portions of the third leads protrude from at least one of the side surfaces of the package body.

5 more elements

Dependencies are inferred from the claim text.