The semiconductor chip (18) of the present invention is a semiconductor chip (18) on which a power semiconductor device (10) is formed, and which includes a semiconductor substrate made from a hexagonal semiconductor, in which the semiconductor substrate has a shape of a rectangle on a principal surface, in which the rectangle is defined by two sides having lengths a and b equal to each other, and in which linear expansion coefficients in directions parallel to the two sides of the semiconductor substrate are equal to each other.
Drawings
Claims17
A semiconductor chip on which a power semiconductor device is formed and which comprises a semiconductor substrate made from a hexagonal semiconductor having an anisotropic property in linear expansion coefficient due to a crystal orientation,
wherein the semiconductor substrate has a shape of a rectangle on a principal surface,
wherein the rectangle is defined by two sides having lengths a and b equal to each other,
wherein linear expansion coefficients in directions parallel to the two sides of the semiconductor substrate are equal to each other, and
wherein the principal surface of the semiconductor substrate and a (0001) plane or (000-1) plane of the hexagonal semiconductor form an angle θ, which satisfies the following expression
−10°≦θ≦10°.
2 more elements
A semiconductor chip on which a power semiconductor device is formed and which comprises a semiconductor substrate made from a hexagonal semiconductor,
wherein the semiconductor substrate has a shape of a rectangle on a principal surface,
wherein the rectangle is defined by two sides having lengths a and b equal to each other, and
wherein one of the two sides and a <11-20> direction of the hexagonal semiconductor form an angle of 15°, and another of the two sides and a <1-100> direction of the hexagonal semiconductor form an angle of 15°.
A semiconductor wafer, comprising:
a wafer made from a hexagonal semiconductor;
and
a plurality of power semiconductor devices formed on the wafer,
wherein the wafer has an anisotropic mechanical property due to crystal orientation on a plane parallel to a principal surface,
wherein the wafer is provided with a mark for determining a crystal direction of the hexagonal semiconductor in at least a part of a circumference of the wafer,
wherein a direction determined by the mark and a <11-20> direction or <1-100> direction of the hexagonal semiconductor form an angle β, which satisfies the following Expression (1):
−5°≦β≦5° (1)
wherein the plurality of power semiconductor devices each has an area defined by a rectangle on the principal surface,
wherein the rectangle is defined by two sides having one side forming an angle γ with the direction determined by the mark, and the angle γ satisfies the following Expression (2) or (2′)
10°≦γ≦20° (2)
40°≦γ≦50° (2′).
8 more elements
A semiconductor wafer, comprising:
a wafer made from a hexagonal semiconductor;
and
a plurality of power semiconductor devices formed on the wafer, wherein the wafer has an anisotropic mechanical property due to crystal orientation on a
plane parallel to a principal surface,
wherein the wafer is provided with a mark for determining a crystal direction of the hexagonal semiconductor in at least a part of a circumference of the wafer,
wherein a direction determined by the mark and a <11-20> direction or <1-100> direction of the hexagonal semiconductor form an angle β′, which satisfies a relation
10°≦β′20°, and
wherein the plurality of power semiconductor devices each has an area defined by a rectangle on the principal surface of the wafer.
5 more elements
A semiconductor chip manufacturing method, comprising the steps of:
dividing a semiconductor wafer, which comprises a wafer made from a hexagonal semiconductor and a plurality of power semiconductor devices formed on the wafer, a plurality of times in parallel to a second direction, which is at an angle of 90° with a first direction, while moving the semiconductor wafer relative to a dividing position of a wafer dividing device for a distance c at a time in the first direction, which is at an angle of 15° with a <11-20> direction or <1-100> direction of the hexagonal semiconductor;
rotating strips of the semiconductor wafer, which are obtained by a division, by 90° relative to the wafer dividing device;
and
dividing the strips of the semiconductor wafer, which are obtained by a division, a plurality of times in parallel to the first direction, while moving the strips of the semiconductor wafer relative to the dividing position of the wafer dividing device for the distance c at a time in the second direction.
13 May 2031Estimated · howhide20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.
Of vertical IGBTs: having a recessed gate, e.g. trench-gate IGBTs
Life of this patent
About 4 years 7 months of term left · ends 13 May 2031 (estimated)
Priority, Japan18 May 2010
Filed13 May 2011
Granted5 Nov 2013
Today12 Oct 2026
Term ends13 May 2031
Priority, Japan18 May 2010
Granted5 Nov 2013
Term ends13 May 2031
Priority claimedJP 2010-114405
Application filedUS 13/579,432
Assigned to Panasonic Corporationassignment of assignor's interest
PublishedUS 2012/0319249 A1
GrantedUS 8,575,729 B2
TodayWithin its term
Term endsEstimated
Description14,544 words
Summary2,369 words
#The present invention relates to a semiconductor chip, a semiconductor wafer, and a semiconductor chip manufacturing method. More particularly, the present invention relates to a semiconductor chip, a semiconductor wafer, and a semiconductor chip manufacturing method that use a hexagonal semiconductor having anisotropic mechanical properties in a direction parallel to a principal surface, such as silicon carbide or gallium nitride.
#In semiconductor devices, there has conventionally been used a silicon (Si) substrate. In recent years, wide-band gap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are attracting attention in the field of power semiconductor devices, and are being developed.
#Wide-band gap semiconductors are semiconductor materials with a high degree of hardness that are wider in band gap than Si. Research is conducted to put into practical use various semiconductor devices that make use of the physical properties of wide-band gap semiconductors, such as power elements, environmentally-resistant elements, high-temperature operating elements, and high-frequency elements. Application of the wide-band gap semiconductors to power elements, in particular, such as switching elements and rectifier elements, is attracting attention, because the power elements that use SiC or GaN have advantages including a significant reduction in power loss as compared to that of Si power elements.
Brief description of the drawings19 figures
#FIGS. 1(a) and 1(b) are plan views each illustrating a semiconductor wafer according to an embodiment of the present invention.
#FIGS. 2(a) and 2(b) are schematic plan views illustrating marks and directions of the semiconductor wafers of FIG. 1(a) and FIG. 1(b), respectively.
#FIG. 3 is a diagram illustrating a <11-20> direction and a <1-100> direction in a hexagonal semiconductor.
Detailed description11,619 words
#In order to assess the reliability of an SiC device, the inventors of the present invention manufactured a 3.6 mm-square power semiconductor device 1010 having a MISFET structure by using, as a semiconductor wafer 1001, a 4H—SiC wafer whose principal surface is off-cut by approximately 4° from a (0001) plane toward a <11-20> direction as illustrated in FIG. 18(a). The symbol “-” attached in front of a numerical value of the Miller index herein represents a bar of the numerical value that follows. For example, the third index of the <11-20> orientation represents “2 bar”. The surface of the power semiconductor device is partially covered with a protective film which uses SiN. The semiconductor wafer 1001 was cut along scribe lines 1020x and 1020y to be broken into semiconductor chips each including the power semiconductor device 1010. The semiconductor chips were then assembled into packages under package assembly conditions A, B, and C which ensures a satisfactory reliability for MISFET structure power semiconductor elements made from Si. The packaged devices were tested by a temperature cycle test which is a common reliability assessment test and in which temperature is repeatedly raised and dropped between −65° C. and 150° C. For comparison, power semiconductor devices were similarly manufactured from Si, assembled into packages, and subjected to the temperature cycle test.
#The package assembly here includes steps of electrically connecting and fixing the semiconductor chip to a metal lead frame with solder or the like, forming an aluminum wire or the like between the lead frame and the semiconductor chip, and sealing the semiconductor chip with an epoxy-based resin material. In general, a polyimide-based material called junction coating resin (JCR) is applied before the power semiconductor element is sealed with resin in some cases.
#Herein, a component part that has a desired function as a device such as a MISFET or a diode is referred to as a power semiconductor element, whereas a component part that includes a power semiconductor element, a perimeter portion formed around the power semiconductor element, and a protective film that covers, at least partially, the power semiconductor element and the perimeter portion is referred to as a power semiconductor device. Pieces of a semiconductor wafer with a plurality of power semiconductor devices formed thereon which are obtained by dividing the semiconductor wafer along scribe lines are referred to as semiconductor chips. The semiconductor chips each include a semiconductor substrate which is a broken piece of the wafer. A structure in which a semiconductor chip is housed in a package is referred to as a semiconductor device.