Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same

A method for fabricating a semiconductor device, comprising:

• forming a device isolation layer on a predetermined region of a semiconductor substrate to define an active region, wherein the active region includes a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer;
• forming a semiconductor pattern on the central top surface and the inclined edge surface of the active region, wherein the semiconductor pattern includes a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall which is substantially perpendicular to the flat top surface;
• and
• forming a gate pattern overlapping the semiconductor pattern.

A method of fabricating a semiconductor device, comprising:

• forming a device isolation layer on a predetermined region of the semiconductor substrate to define a first active region and a second active region, wherein at least the first active region out of the first and second active regions includes a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer;
• forming a first semiconductor pattern and a second semiconductor pattern respectively on the first and the second active regions, wherein the first semiconductor pattern includes a flat top surface of (100) crystal plane parallel with the central top surface of the first active region and a sidewall substantially perpendicular to the flat top surface of the first active region, and the second semiconductor pattern includes a lower semiconductor pattern having a first band gap energy and an upper semiconductor pattern having a second band gap energy that is different from the first band gap energy;
• and
• forming a first gate pattern and a second gate pattern overlapping the first and the second semiconductor patterns, respectively.