Insulated gate bipolar transistor structure having low substrate leakage

A high voltage semiconductor transistor, comprising:

• a lightly doped semiconductor substrate having a first type of conductivity, wherein a portion of the lightly doped semiconductor substrate includes an oxygen layer below a top surface of the lightly doped semiconductor substrate;
• a first well region having a second type of conductivity over the lightly doped semiconductor substrate;
• a second well region having the first type of conductivity in the first well region, wherein the second well region comprises:
• a first portion having a top surface co-planar with a top surface of the first well region, and
• a second portion extending parallel to the top surface of the first well region at a depth below the top surface of the first well region;
• an insulating structure over and partially embedded in the first well region;
• a gate structure having a first portion over the first well region, and a second portion over the second well region;
• a drain region in the first well region on an opposite side of the insulating structure from the gate structure, the drain region comprising a first drain portion and a second drain portion separated from the first drain portion, wherein the first drain portion has the first type of conductivity and the second drain portion has the second type of conductivity;
• a source region in the first portion of the second well region disposed on a side of the gate structure opposite from the drain region;
• and
• a deep trench isolation feature in the first well region surrounding at least the second well region, the insulating structure, the gate structure, and the source region, wherein the deep trench isolation feature contacts the oxygen layer.

A high voltage semiconductor transistor, comprising:

• a lightly doped semiconductor substrate having a first type of conductivity, wherein a portion of the lightly doped semiconductor substrate includes an oxygen layer having a top surface at least 100 nanometers (nm) below a top surface of the lightly doped semiconductor substrate;
• a first well region having a second type of conductivity over the lightly doped semiconductor substrate;
• a second well region in the first well region and having the first type of conductivity;
• an insulating structure over and partially embedded in the first well region;
• a gate structure over the first well region and the second well region;
• a drain region in the first well region across the insulating structure from the gate structure, the drain region comprising a first drain portion adjacent to the insulating structure and a second drain portion separated from the insulating structure by the first drain portion, wherein the first drain portion has the first type of conductivity and the second drain portion has the second type of conductivity;
• a source region in the second well region disposed on a side of the gate structure opposite from the drain region;
• and
• a deep trench isolation feature in the first well region separating the first drain portion from the second drain portion, wherein the deep trench isolation feature contacts the oxygen layer.