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US 8,575,668 B2Granted
Charge breakdown avoidance for MIM elements in SOI base technology and method
AssigneeInternational Business Machines Corporation
InventorsWilliam F. Clark, Jr., Stephen E. Luce
Life of this patent
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Abstract
A semiconductor device including at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate. A method of fabricating a semiconductor structure includes forming an SOI substrate, forming a BOX layer over the SOI substrate, and forming at least one capacitor in wiring levels on the BOX layer, wherein the at least one capacitor is coupled to an active layer of the SOI substrate.
Claims18
A semiconductor structure, comprising:
- at least one capacitor formed in wiring levels on a silicon-on-insulator (SOI) substrate, which is coupled to an active layer of the SOI substrate, wherein the at least one capacitor is a metal-on-insulator (MIM) capacitor and wherein MIM plates of the MIM capacitor are tied to a back-to-back lateral diode circuit, whereby capacitor breakdown is clamped to a base-to-emitter voltage (VBE) above diode breakdown.
A semiconductor structure, comprising:
- a silicon-on-insulator (SOI) substrate;
- a buried oxide (BOX) layer formed on the SOI substrate;
- and
- at least one capacitor formed in wiring levels on the silicon-on-insulator (SOI) substrate, wherein the at least one capacitor is coupled to an active layer of the SOI substrate,
- wherein the at least one capacitor is a metal-on-insulator (MIM) capacitor and wherein MIM plates of the MIM capacitor are tied to a back-to-back lateral diode circuit, whereby capacitor breakdown is clamped to a base-to-emitter voltage (VBE) above diode breakdown.
2 more elements
Dependencies are inferred from the claim text.