Method and structure having monolithic heterogeneous integration of compound semiconductors with elemental semiconductor

A semiconductor structure having CMOS transistors and a compound semiconductor device, comprising:

• a column III-V semiconductor growth support;
• a column III-V semiconductor device disposed on the support;
• selective etch layer is disposed over the compound semiconductor growth support;
• wherein the selective etch layer has a lower etch rate to a fluorine containing plasma etch than the etch rate of the dielectric layer has to the fluorine containing plasma etch, wherein the selective etch layer is aluminum oxide (Al2O3), aluminum nitride (AlN), or a plurality of layers having combinations of aluminum oxide (Al2O3), aluminum nitride (AlN);
• a silicon layer is disposed over the selective etch layer, the silicon layer having disposed in portions thereof the CMOS transistors;
• wherein a window formed through other portions of the silicon layer and underlying portions of the selective etch layer exposes a portion of the compound semiconductor growth support;
• and
• wherein the compound semiconductor is disposed on the exposed portion of the compound semiconductor growth support.