Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering
AssigneeInternational Business Machines Corporation
InventorsStephen W. Bedell, Ashima B. Chakravarti, Michael P. Chudzik, Judson R. Holt, Dominic J. Schepis
Life of this patent
Estimating the term…
Abstract
Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
Claims19
A structure including a SiGe engineered channel comprising:
- a semiconductor substrate having at least one active area with an exposed upper surface comprising a semiconductor material of said semiconductor substrate, wherein isolation regions are present in said semiconductor material and are located at a periphery of said at least one active device region, each isolation region having an upper surface that is coplanar with the exposed upper surface of the semiconductor material;
- and
- a SiGe film located directly on the exposed upper surface of the semiconductor material active area, said SiGe film including a lower region that has a first Ge concentration and an upper region that has a second Ge concentration, wherein the first Ge concentration is greater than the second Ge concentration, and wherein said SiGe film has sidewall surfaces located above the isolation regions, wherein each sidewall surface of said SiGe film is oriented perpendicular to a topmost surface of the semiconductor substrate and is vertically aligned to a sidewall edge of each isolation region that is located at the periphery of the at least one active device region.
A structure including a SiGe engineered channel comprising:
- a semiconductor substrate having at least one active area with an exposed upper surface of a semiconductor material of said semiconductor substrate, wherein isolation regions are present in said semiconductor material and are located at a periphery of said at least one active device region, each isolation region having an upper surface that is coplanar with the exposed upper surface of the semiconductor material;
- a SiGe film located directly on the exposed upper surface of the semiconductor material active area, said SiGe film including a lower region that has a first Ge concentration and an upper region that has a second Ge concentration, wherein the first Ge concentration is greater than the second Ge concentration, and wherein said SiGe film has sidewall surfaces located above the isolation regions, wherein each sidewall surface of SiGe film is oriented perpendicular to a topmost surface of the semiconductor substrate and is vertically aligned to a sidewall edge of each isolation region that is located at the periphery of the at least one active device region;
- and
- a p-type field effect transistor (pFET) located atop said SiGe film, said pFET comprising:
- a gate dielectric and an overlying gate conductor, said gate dielectric having a higher dielectric constant than SiO2, and
- a source region and a drain region located within said SiGe film and extending into an upper portion of said semiconductor substrate, wherein a portion of said SiGe film located between said source region and said drain region is a channel region of said pFET.
Dependencies are inferred from the claim text.