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US 8,575,652 B2Granted
Semiconductor device and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorYoshiki Kamata
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AssigneeKabushiki Kaisha Toshiba
InventorYoshiki Kamata
Estimating the term…
An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.
A semiconductor device comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
No references of this kind are recorded.
Of igfets: inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
Manufacture or treatment: of FETs having insulated gates [IGFET]
Of electrodes having a conductor capacitively coupled to a semiconductor by an insulator: the insulator being formed after the semiconductor body,…
Characterised by the semiconductor materials: into Group IV semiconductors
About 3 years 6 months of term left · ends 30 Apr 2030 (estimated)
This application is based upon and claims the benefit of priority from a Japanese Patent Application No. 2008-17118, filed on Jan. 29, 2008, the entire contents of which are incorporated herein by reference.
Described herein is a semiconductor device in which a source/drain impurity layer is formed in a semiconductor region containing Ge and a method for manufacturing the semiconductor device.
Improvement of performance of MISFET has been achieved by a scaling-down technique. However, because the scaling-down technique is approaching the limit, the technique of improving the performance of MISFET except for the scaling-down technique is studied. The use of a substrate except for a Si substrate which has electron or hole mobility higher than that of Si, for example, the use of a SiGe substrate or a Ge substrate is studied. Also studied is a technique embedding SiGe or Ge in a source/drain region, and applying a distortion to Si channel, thereby improving the carrier mobility in the Si channel.
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment.
FIGS. 2 to 5 are sectional views showing a process of manufacturing the semiconductor device of the first embodiment.
FIG. 6 shows a rectifying characteristic of a p+/n− junction in the first embodiment.
Embodiments will be described below with reference to the drawings.
(First Embodiment)
A semiconductor device according to a first embodiment has MISFET including a channel region which is formed in a semiconductor substrate containing Ge; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the MISFET, the source/drain impurity layer is formed in the semiconductor substrate containing Ge, and at least a kind of an element selected from S (sulfur), Se (selenium), and Te (tellurium) is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.