Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorsTakahisa Kanemura, Masaki Kondo
Life of this patent
Estimating the term…
Abstract
In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.
Claims16
A semiconductor device comprising:
- a semiconductor substrate;
- a gate electrode provided on the semiconductor substrate via an insulating layer;
- a gate insulator provided on a side surface and an upper surface of the gate electrode;
- a semiconductor layer provided on the side surface and the upper surface of the gate electrode via the gate insulator;
- and
- a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer,
- wherein the upper main terminal layer is provided on the side surface and the upper surface of the gate electrode via the gate insulator and the semiconductor layer.
A semiconductor device comprising:
- a semiconductor substrate;
- a gate electrode provided on the semiconductor substrate via an insulating layer;
- a gate insulator provided on a side surface of the gate electrode;
- first and second semiconductor layers provided on the side surface of the gate electrode via the gate insulator;
- and
- a stacked layer including a first lower main terminal layer of a first conductivity type, a first intermediate layer, a first upper main terminal layer of a second conductivity type, an insulator, a second lower main terminal layer of the first conductivity type, a second intermediate layer, and a second upper main terminal layer of the second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator and the first and second semiconductor layers,
- wherein
- the first lower main terminal layer, the first intermediate layer and the first upper main terminal layer are provided on the side surface of the gate electrode via the gate insulator and the first semiconductor layer,
- the second lower main terminal layer, the second intermediate layer and the second upper main terminal layer are provided on the side surface of the gate electrode via the gate insulator and the second semiconductor layer, and
- the first and second semiconductor layers are separated from each other by the gate insulator.
A semiconductor device comprising:
- a semiconductor substrate;
- a gate electrode provided on the semiconductor substrate via an insulating layer;
- a gate insulator provided on a side surface of the gate electrode;
- first and second semiconductor layers provided on the side surface of the gate electrode via the gate insulator;
- and
- a stacked layer including a first lower main terminal layer of a first conductivity type, a first intermediate layer, a first upper main terminal layer of a second conductivity type, an insulator, a second lower main terminal layer of the second conductivity type, a second intermediate layer, and a second upper main terminal layer of the first conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator and the first and second semiconductor layers,
- wherein
- the first lower main terminal layer, the first intermediate layer and the first upper main terminal layer are provided on the side surface of the gate electrode via the gate insulator and the first semiconductor layer,
- the second lower main terminal layer, the second intermediate layer and the second upper main terminal layer are provided on the side surface of the gate electrode via the gate insulator and the second semiconductor layer, and
- the first and second semiconductor layers are separated from each other by the gate insulator.
Dependencies are inferred from the claim text.