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US 8,575,621 B1Granted
Low interconnect resistance integrated switches
AssigneeSarda Technologies, Inc.
InventorJames L. Vorhaus
Life of this patent
Estimating the term…
Abstract
Circuits and systems comprising one or more switches are provided. A circuit includes a first switch formed on a substrate; and a second switch formed on the substrate, the second switch including a first terminal coupled to a third terminal of the first switch. A system includes a supply; a first switch formed on a substrate, the first switch coupled to the supply; a second switch formed on the substrate, the second switch coupled to the first switch; a third switch formed on the substrate, the third switch coupled to the supply; a fourth switch formed on the substrate, the fourth switch coupled to the third switch; and a driver coupled to respective second terminals of the first, second, third, and fourth switches.
Claims21
A dual Field Effect Transistor (FET) comprising:
- a control switch formed on a substrate, the control switch including:
- a control drain terminal configured to receive power from a first power supply node and distribute the received power to a control drain finger,
- a control source terminal configured to couple a control source finger to a load, and
- a control gate terminal coupled through a control gate pad to a control gate finger disposed between the control drain finger and the control source finger, the control gate terminal configured to receive a control gate signal for switching current between the control drain finger and the control source finger;
- and
- a sync switch formed on the substrate, the sync switch including:
- a sync source terminal configured to receive power from a second power supply node and distribute the power to a sync source finger,
- a sync drain finger contiguous with the control source finger to form a single continuous ohmic finger, and
- a sync gate terminal coupled through a sync gate pad to a sync gate finger disposed between the sync drain finger and the sync source finger, the sync gate terminal configured to receive a sync gate signal for switching current between the sync drain finger and the sync source finger, the control gate pad and the sync gate pad disposed between the control drain finger and the sync source finger.
6 more elements
A dual Field Effect Transistor device comprising:
- a plurality of hybrid ohmic metal fingers disposed on a semiconductor material, each hybrid ohmic metal finger including both a sync region and a contiguous control region disposed continuously along a width of the hybrid ohmic metal finger;
- a plurality of sync ohmic metal fingers disposed along the sync region of the width of the hybrid ohmic metal fingers and alternating with the sync region of the hybrid ohmic metal fingers;
- a plurality of control ohmic metal fingers disposed along the control region of the width of the hybrid ohmic metal fingers and alternating with the control region of the hybrid ohmic metal fingers, the sync ohmic metal fingers aligned with the control ohmic metal fingers;
- a plurality of sync gate fingers disposed between the sync ohmic metal fingers and sync region of the hybrid ohmic metal fingers for switching current between the sync ohmic metal fingers and the sync region of the hybrid ohmic metal finger;
- and
- a plurality of control gate fingers disposed between the control ohmic metal fingers and the control region of the hybrid ohmic metal fingers for switching current between the control ohmic metal fingers and the control region of the hybrid ohmic metal finger.
3 more elements
A dual Field Effect Transistor (FET) comprising:
- a plurality of dual ohmic metal fingers disposed on a semiconductor material, each dual ohmic metal finger including both a first FET region and a contiguous second FET region disposed continuously along a width of the dual ohmic metal finger;
- a plurality of first FET ohmic metal fingers disposed along a width of the first FET region of the dual ohmic metal fingers and alternating with the first FET region of the dual ohmic metal fingers;
- a plurality of second FET ohmic metal fingers disposed along a width of the second FET region of the dual ohmic metal fingers and alternating with the second FET region of the dual ohmic metal fingers, the first FET ohmic metal fingers aligned with the second FET ohmic metal fingers;
- a plurality of first FET gate fingers disposed between the first FET ohmic metal fingers and the first FET region of the dual ohmic metal fingers for switching current between the first FET ohmic metal fingers and the first FET region of the dual ohmic metal finger;
- and
- a plurality of second FET gate fingers disposed between the second FET ohmic metal fingers and second FET region of the dual ohmic metal fingers for switching current between the second FET ohmic metal fingers and the second FET region of the dual ohmic metal finger.
3 more elements
A method for switching current using a Field Effect Transistor (FET), the method comprising:
- receiving a control gate signal at both ends of a control gate finger;
- switching a plurality of distributed of control current segments between a plurality of control drain sections disposed along a control drain element and a plurality of control source sections disposed along a control source element using the received control gate signal;
- conducting the switched current segments from the control source element to a sync drain element through a continuous ohmic metal finger, the control source element and the sync drain element being contiguous sections along the width of the continuous ohmic metal finger;
- receiving a sync gate signal at both ends of a sync gate finger;
- and
- switching a plurality of distributed of sync current segments between a plurality of sync drain sections disposed along the sync drain element and a plurality of sync source sections disposed along a sync source element using the received control gate signal.
3 more elements
Dependencies are inferred from the claim text.