Semiconductor memory device
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorYasuyuki Arai
Life of this patent
Estimating the term…
Abstract
An object is to provide a semiconductor memory device which can be miniaturized and also secures a sufficient margin for the refresh period. A memory cell includes a reading transistor, a writing transistor, and a capacitor. In the above structure, the capacitor controls a potential applied to a gate of the reading transistor. The writing transistor controls writing and erasing of data and, when the transistor is off, has small current so that loss of electric charges stored in the capacitor, which is due to leakage current of the writing transistor, can be prevented. A semiconductor layer included in the writing transistor is provided so as to extend from the gate electrode toward a source region of the reading transistor. The capacitor is provided to overlap with the gate electrode of the reading transistor.
Claims8
A semiconductor memory device comprising a memory cell,
- the memory cell comprising:
- a first transistor, the first transistor comprising:
- a first semiconductor layer in which a first impurity region and a second impurity region are formed;
- a first gate electrode formed over the first semiconductor layer;
- a first insulating layer formed between the first gate electrode and the first semiconductor layer;
- and
- a second insulating layer and a third insulating layer formed on a side wall portion of the first gate electrode;
- a second transistor, the second transistor comprising:
- a second semiconductor layer formed on the third insulating layer, wherein the second semiconductor layer is in contact with the first electrode and the first impurity region;
- a fourth insulating layer on the second semiconductor layer, the fourth insulating layer extending over an upper surface of the first gate electrode;
- and
- a second gate electrode formed over the second semiconductor layer with the fourth insulating layer interposed therebetween;
- and
- a capacitor comprising the first gate electrode, the fourth insulating layer over the first gate electrode, and an electrode formed over the first gate electrode with a portion of the fourth insulating layer interposed therebetween.
A semiconductor memory device comprising:
- a first transistor, the first transistor comprising:
- a first semiconductor layer in which a first impurity region and a second impurity region forming a source region and a drain region are formed;
- a first gate electrode formed over the first semiconductor layer;
- a first insulating layer formed between the first gate electrode and the first semiconductor layer;
- and
- a second insulating layer and a third insulating layer formed on a side wall portion of the first gate electrode;
- a second transistor, the second transistor comprising:
- a second semiconductor layer formed on the third insulating layer, wherein the second semiconductor layer is in contact with the first electrode and the first impurity region;
- a fourth insulating layer on the second semiconductor layer, the fourth insulating layer extending over an upper surface of the first gate electrode;
- and
- a second gate electrode formed over the second semiconductor layer and the fourth insulating layer so as to overlap with the third insulating layer;
- and
- a capacitor comprising the first gate electrode, the fourth insulating layer over the first gate electrode, and an electrode formed to over the first gate electrode with a portion of the fourth insulating layer interposed therebetween,
- wherein the first impurity region is connected to a bit line,
- wherein the second impurity region is connected to a common potential line,
- wherein the second gate electrode is connected to a first word line, and
- wherein the electrode of the capacitor is connected to a second word line.
Dependencies are inferred from the claim text.