Resistive memory device having vertical transistors and method for making the same

A resistive memory device comprising:

• a silicon substrate having a first type conductivity;
• a plurality of vertical selection transistors formed on said silicon substrate in an array, each of said plurality of vertical selection transistors including:
• a silicon pillar protruded from said silicon substrate, top region of said silicon pillar having a second type conductivity opposite to the first type conductivity provided in said silicon substrate;
• and
• a doped polysilicon gate electrode surrounding said silicon pillar with a silicon oxide gate dielectric layer interposed therebetween, said doped polysilicon gate electrode being lower in height than said silicon pillar;
• a plurality of contact studs with each contact stud being self-aligned to the top region one of the semiconductor pillars and providing Ohmic contact for one of said vertical selection transistors;
• a plurality of resistive memory elements disposed on top of said contact studs;
• a plurality of parallel word lines with each word line connecting a row of gate electrodes of said vertical selection transistors, said parallel word lines extending along a first direction and being monolithic with the gate electrodes;
• a plurality of parallel bit lines respectively connecting rows of said resistive memory elements, said parallel bit lines extending along a second direction different from the first direction provided in said parallel word lines;
• and
• a plurality of parallel source lines with the second type conductivity formed in top regions of said semiconductor substrate with each source line being disposed parallel to and in between word lines connecting adjacent rows of said vertical selection transistors,
• wherein said vertical selection transistors are arranged in a square array with a pitch of 2F, each of said word lines and said row of gate electrodes connected thereto have a monolithic structure, and a pair of said source lines function as common source for adjacent rows of rows of said vertical selection transistors.

A method for fabricating a resistive memory device comprising the steps of:

• providing a semiconductor substrate having a first type conductivity;
• forming a plurality of semiconductor pillars on said substrate with top regions of said pillars having a second type conductivity opposite to the first type conductivity;
• depositing a conformal gate dielectric layer over the substrate and around peripheries of said semiconductor pillars;
• depositing a conformal layer of conductive material over the gate dielectric layer and around the peripheries of said semiconductor pillars;
• selectively dry etching the layer of conductive material to remove the conductive material from tops of said semiconductor pillars and from parallel strips between said semiconductor pillars to form a plurality of self-aligned gate electrodes around said semiconductor pillars with said gate dielectric layer interposed therebetween and to form a plurality of parallel word lines connecting said gate electrodes that are monolithic with said gate electrodes, said gate electrodes being lower in height than said semiconductor pillars;
• forming a plurality of parallel source lines in top regions of said substrate in between and parallel to said word lines by ion implantation, said source lines having the second type conductivity and thereby forming source lines that are common to adjacent word lines;
• forming a plurality of self-aligned contact studs on said semiconductor pillars;
• forming a plurality of resistive memory elements on said contact studs;
• and
• forming a plurality of parallel bit lines extending perpendicular to the source lines and connecting rows of said resistive memory elements.