Image sensor array for back side illumination with global shutter using a junction gate photodiode

A method for controlling a junction gate photo-diode (JGP) pixel, the pixel comprising a JGP, the JGP positioned on a substrate including a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer, a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier, a pinned barrier (PB) and a storage gate (SG) positioned on the substrate between the JGP and the FD, a clearing gate (CG) positioned on the substrate adjacent to the JGP, a reset gate positioned on the substrate and coupled to the FD, and a controller, the method comprising:

• applying, by the controller, during a reset period, a reset control voltage to the reset gate to clear charge accumulated in the FD, and a clearing control voltage to the CG to clear charge accumulated in the JGP,
• applying, by the controller, during an integration period, an integration control voltage to the JGP to accumulate charge in the JGP, a transfer control voltage to the JGP and another transfer control voltage to the SG to transfer the accumulated charge from the JGP to the SG, and a storage control voltage to the SG to store the transferred charge in the SG, and
• applying, by the controller, during a readout period, a readout control voltage to the SG to transfer the charge stored in the SG over the PB and into the FD for pixel readout.

A method for forming a junction gate photo-diode (JGP) pixel on a substrate, the method comprising:

• forming a JGP on a substrate, the JGP including a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer, the JGP accumulating charge in response to impinging photons;
• forming a floating diffusion (FD) on the substrate;
• forming a pinned barrier (PB) and a storage gate (SG) on the substrate between the JGP and the FD;
• and
• forming pixel wiring on the substrate above the JGP, FD, SG and PB, the pixel wiring coupled to the JGP, FD, SG and PB,
• wherein the PB temporarily blocks charge transfer between the JGP and the FD, the SG receives the accumulated charge from the JGP, stores the charge in the SG, and transfers the stored charge to the FD.