Contact formation method, semiconductor device manufacturing method, and semiconductor device
AssigneesNational University Corporation Tohoku University, Foundation for Advancement of International Science
InventorsTadahiro Ohmi, Akinobu Teramoto, Tatsunori Isogai, Hiroaki Tanaka
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Abstract
A semiconductor device manufacturing method which achieves a contact of a low resistivity is provided. In a state where a first metal layer in contact with a semiconductor is covered with a second metal layer for preventing oxidation, only the first metal layer is silicided to form a silicide layer with no oxygen mixed therein. As a material of the first metal layer, a metal having a work function difference of a predetermined value from the semiconductor is used. As a material of the second metal layer, a metal which does not react with the first metal layer at an annealing temperature is used.
Claims51
A method of forming a contact of a metal semiconductor compound on a predetermined region of a semiconductor device, comprising the steps of:
- selecting a first metal in relation to a semiconductor type of the predetermined region;
- forming a layer of the first metal on the predetermined region;
- forming, on the layer of the first metal, a layer of a second metal for preventing oxidation of the first metal;
- and
- compounding only the first metal with a semiconductor by heat treatment while the first metal is covered with the layer of the second metal, to thereby form the contact of the metal semiconductor compound which has a contact resistance of 10−9Ωcm2 or less;
- wherein, when the predetermined region is an n-type semiconductor region, the first metal is selected from a metal which has a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of the semiconductor;
- wherein, when the predetermined region is a p-type semiconductor region, the first metal is selected from a metal which has a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of an energy level at the top of a valence band of the semiconductor;
- and
- wherein the second metal is of tungsten while the layer of the second metal has a thickness between 50 nm and 300 nm.
A semiconductor device manufacturing method comprising the steps of:
- forming a layer of a first metal at a silicon portion to be a p-type or an n-type contact region of a semiconductor device;
- forming, on the layer of the first metal, a layer of a second metal for preventing oxidation of the first metal;
- and
- forming a silicide of the first metal by reacting only the first metal with the silicon portion while the first metal is covered with the layer of the second metal to thereby form the silicide of the first metal with the silicon which has a contact resistance of 10−9Ωcm2 or less;
- wherein:
- when the contact region is of an n-type, a metal which is selected and used as the first metal has a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of silicon, and
- wherein:
- when the contact region is of a p-type, the metal which is selected and used as the first metal has a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of an energy level at the top of a valence band of silicon;
- wherein the second metal is of tungsten while the thickness of the second metal has a thickness between 50 nm and 300 nm.
A semiconductor device comprising:
- a silicide layer of a silicide of a first metal formed on a surface of a silicon portion as a p-type or an n-type contact region of the semiconductor device;
- and
- a layer of a second metal formed on the silicide layer to prevent oxidation of the first metal;
- wherein, when the contact region is of the n-type, the silicide layer is formed by the first metal which has a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of silicon,
- wherein, when the contact region is of the p-type, the silicide layer is formed by the first metal which has a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of an energy level at the top of a valence band of silicon;
- and
- wherein the silicide layer has a contact resistance of 10−9Ωcm2 or less;
- wherein the second metal is of tungsten while the layer of the second metal has a thickness between 50 nm and 300 nm.
A semiconductor device comprising a silicide layer of a silicide of a first metal formed on a surface of a silicon portion as a p-type or an n-type contact region of the semiconductor device;
- wherein:
- when the contact region is of the n-type, the silicide layer is formed by the first metal which has a work function whose absolute value is smaller than a value obtained by adding 0.3 eV to an absolute value of an energy level at the bottom of a conduction band of silicon,
- wherein:
- when the contact region is of the p-type, the silicide layer is formed by the first metal which has a work function whose absolute value is greater than a value obtained by subtracting 0.3 eV from an absolute value of an energy level at the top of a valence band of silicon;
- wherein the amount of mixed oxygen in the silicide layer is 1 mass% or less;
- and
- wherein the silicide layer has a contact resistance of 10−9Ωcm2 or less.
An n-MOS transistor comprising a source electrode and a drain electrode each of which includes a laminated structure comprising a holmium silicide layer and a tungsten layer formed thereon and each of which is formed on an n-type silicon region
- wherein the holmium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer has a thickness such that the holmium silicide layer has a predetermined flatness.
A p-MOS transistor comprising a source electrode and a drain electrode each of which includes a laminated structure comprising a palladium silicide layer and a tungsten layer formed thereon and each of which is formed on a p-type silicon region;
- wherein the palladium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- wherein the tungsten layer has a thickness such that the palladium silicide layer has predetermined flatness.
A CMOS semiconductor device comprising an n-MOS transistor and a p-MOS transistor, the n-MOS transistor comprising a source electrode and a drain electrode each of which includes a laminated structure comprising a holmium silicide layer and a tungsten layer formed thereon and each of which is formed on an n-type silicon region, the p-MOS transistor comprising a source electrode and a drain electrode each of which includes a palladium silicide layer and each of which is formed on a p-type silicon region
- wherein each of the holmium silicide layer and the palladium silicide layer has a contact resistance of 10−9Ωcm2 or less.
An inversion mode n-MOS transistor comprising a gate electrode which includes a laminated structure comprising a zirconium layer and a tungsten layer formed thereon and which is formed on a gate insulating film;
- and
- a source electrode and a drain electrode each of which includes a laminated structure comprising a holmium silicide layer and a tungsten layer formed thereon and each of which is formed on an n-type silicon region;
- wherein the holmium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer has a thickness such that the holmium silicide layer has a predetermined flatness.
An accumulation mode p-MOS transistor comprising a gate electrode which includes a laminated structure comprising a zirconium layer and a tungsten layer formed thereon and which is formed on a gate insulating film;
- and
- a source electrode and a drain electrode each of which includes a laminated structure comprising a palladium silicide layer and a tungsten layer formed thereon and each of which is formed on a p-type silicon region;
- wherein the palladium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer on the palladium silicide layer has a thickness such that the holmium silicide layer has a predetermined flatness.
An inversion mode p-MOS transistor comprising a gate electrode which includes a laminated structure comprising a palladium layer and a tungsten layer formed thereon and which is formed on a gate insulating film;
- and
- a source electrode and a drain electrode each of which includes a laminated structure comprising a palladium silicide layer and a tungsten layer formed thereon and each of which is formed on a p-type silicon region;
- wherein the palladium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer on the palladium silicide layer has a thickness such that the holmium silicide layer has a predetermined flatness.
An accumulation mode n-MOS transistor comprising a gate electrode which includes a laminated structure comprising a palladium layer and a tungsten layer formed thereon and which is formed on a gate insulating film;
- and
- a source electrode and a drain electrode each of which includes a laminated structure comprising a holmium silicide layer and a tungsten layer formed thereon and each of which is formed on an n-type silicon region;
- wherein the holmium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer on the holmium silicide layer has a thickness such that the holmium silicide layer has a predetermined flatness.
An inversion mode n-MOS transistor comprising a gate electrode which includes a laminated structure comprising a zirconium layer and a tungsten layer formed thereon and which is formed on a gate insulating film, and a source electrode and a drain electrode each of which includes a laminated structure comprising a holmium silicide layer and a tungsten layer formed thereon and each of which is formed in an n-type silicon region
- wherein the holmium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer on the holmium silicide layer has a thickness such that the holmium silicide layer has a predetermined flatness.
An accumulation mode p-MOS transistor comprising:
- a gate electrode which includes a laminated structure comprising a zirconium layer and a tungsten layer formed thereon and which is formed on a gate insulating film, and
- a source electrode and a drain electrode each of which includes a single layer structure of palladium silicide or a laminated structure comprising a palladium silicide layer and a tungsten layer formed thereon and each of which is formed in a p-type silicon region;
- wherein the palladium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer on the palladium silicide layer has a thickness such that the palladium silicide layer has a predetermined flatness.
An inversion mode p-MOS transistor comprising:
- a gate electrode which includes a laminated structure comprising a palladium layer and a tungsten layer formed thereon and which is formed on a gate insulating film, and
- a source electrode and a drain electrode each of which includes a single layer structure of palladium silicide or a laminated structure comprising a palladium silicide layer and a tungsten layer formed thereon and each of which is formed in a p-type silicon region;
- wherein the palladium silicide layer has a contact resistance of 10−9Ωcm2 or less:
- and
- wherein the tungsten layer on the palladium silicide layer has a thickness such that the palladium silicide layer has a predetermined flatness.
An accumulation mode n-MOS transistor comprising:
- a gate electrode which includes a laminated structure comprising a palladium layer and a tungsten layer formed thereon and which is formed on a gate insulating film, and
- a source electrode and a drain electrode each of which includes a laminated structure comprising a holmium silicide layer and a tungsten layer formed thereon and each of which is formed in an n-type silicon region;
- wherein the holmium silicide layer has a contact resistance of 10−9Ωcm2 or less;
- and
- wherein the tungsten layer on the holmium silicide layer has a thickness such that the holmium silicide layer has a predetermined flatness.
Dependencies are inferred from the claim text.