Contact architecture for 3D memory array
AssigneeMacronix International Co., Ltd.
InventorsShih-Hung Chen, Yen-Hao Shih, Hang-Ting Lue
Life of this patent
Estimating the term…
Abstract
A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.
Claims26
A method for manufacturing a memory device, the method comprising:
- forming a plurality of stacks of conductive strips separated by insulating material;
- forming vertical connectors interconnecting first ends of the conductive strips of respective stacks in the plurality of;
- forming a memory layer on surfaces of the conductive strips of the stacks;
- forming conductive material over the stacks and on top surfaces of the vertical connectors;
- and
- patterning the conductive material to form a plurality of conductive lines and form contact pads, the plurality of conductive lines extending across, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the conductive strips and the plurality of conductive lines, and the contact pads on the top surfaces of the vertical connectors, wherein the contact pads and conductive material of the conductive lines are part of the same patterned level of material, such that memory elements in the memory layer are defined in the interface regions, thereby establishing a 3D array of memory cells accessible via the plurality of conductive lines and the contact pads.
A memory device comprising:
- a plurality of stacks of conductive strips separated by insulating material;
- vertical connectors interconnecting first ends of the conductive strips of respective stacks in the plurality of stacks;
- a plurality of conductive lines extending across, and having surfaces conformal with, the plurality of stacks, such that a 3D array of interface regions is established at cross-points between surfaces of the conductive strips and the plurality of conductive lines;
- contact pads on top surfaces of the vertical connectors, wherein the contact pads and conductive material of the conductive lines are part of the same patterned level of material;
- and
- memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of conductive lines and the contact pads.
Dependencies are inferred from the claim text.