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US 8,574,991 B2Granted
Asymmetric transistor devices formed by asymmetric spacers and tilted implantation
AssigneeGlobalfoundries Inc.
InventorsJan Hoentschel, Uwe Griebenow, Maciej Wiatr
Life of this patent
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Abstract
An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
Claims13
A method, comprising:
- performing a non-zero tilt angle implantation process to form at least one of asymmetric counter doped regions and asymmetric shallow extension regions of drain and source regions of a transistor in a semiconductor region, said semiconductor region having a gate electrode formed thereabove;
- after forming said at least one of asymmetric counter doped regions and asymmetric extension regions, asymmetrically forming a spacer element on sidewalls of said gate electrode, wherein asymmetrically forming said spacer element comprises depositing a spacer material, covering said spacer material at one of a drain side and a source side of said transistor by an implantation mask, implanting an implantation species so as to modify an etch behavior of an exposed portion of said spacer material and etching said spacer material after removing said implantation mask;
- and
- forming deep drain and source areas of said drain and source regions using said asymmetrically formed spacer element.
1 more element
A method, comprising:
- forming a gate electrode above an active region of a transistor element;
- forming asymmetric shallow source and drain extension regions in said active region using said gate electrode as an implantation mask during a non-zero tilt angle implantation sequence;
- forming a layer of spacer material above said gate electrode and said active region;
- forming a patterned implantation mask above said layer of spacer material, said patterned implantation mask exposing a portion of said layer of spacer material adjacent to a first sidewall of said gate electrode and covering a portion of said layer of spacer material adjacent to a second sidewall of said gate electrode;
- performing an ion implantation process using said patterned implantation mask so as to asymmetrically modifying an etch behavior of said layer of spacer material relative to said sidewalls of said gate electrode;
- forming asymmetric spacer structures on sidewalls of said gate electrode by performing an etch process on said layer of spacer material having said asymmetrically modified etch behavior;
- and
- forming deep source and drain regions in said active region using said asymmetric spacer structures as an implantation mask during a source/drain implantation process.
5 more elements
A method, comprising:
- performing a non-zero tilt angle implantation process to form at least one of asymmetric counter doped regions and asymmetric shallow extension regions of drain and source regions of a transistor in a semiconductor region, said semiconductor region having a gate electrode formed thereabove;
- after forming said at least one of asymmetric counter doped regions and asymmetric extension regions, asymmetrically forming a spacer element on sidewalls of said gate electrode, wherein asymmetrically forming said spacer element comprises depositing a spacer material, covering said spacer material at a first one of a drain side and a source side of said transistor by a mask and using said mask as an etch mask while performing an etch process to etch said spacer material at a second one of said drain side and said source side;
- and
- forming deep drain and source areas of said drain and source regions using said asymmetrically formed spacer element.
1 more element
Dependencies are inferred from the claim text.