US 8,574,989 B2 · Semiconductor structure having a polysilicon structure and method of forming same

Abstract

The present application discloses a method of forming a semiconductor structure. In at least one embodiment, the method includes forming a polysilicon layer over a substrate. A mask layer is formed over the polysilicon layer. The mask layer is patterned to form a patterned mask layer. A polysilicon structure is formed by etching the polysilicon layer using the patterned mask layer as a mask. The polysilicon structure has an upper surface and a lower surface, and the etching of the polysilicon layer is arranged to cause a width of the upper surface of the polysilicon structure greater than that of the lower surface of the polysilicon structure.

Claims20

Dependent claims

A method of forming a semiconductor structure comprising:

forming a polysilicon layer over a substrate;
forming a mask layer over the polysilicon layer;
patterning the mask layer to form a patterned mask layer;
forming a polysilicon structure by etching the polysilicon layer using the patterned mask layer as a mask;
and
forming a dielectric layer over the substrate and surrounding the polysilicon structure, wherein the dielectric layer is arranged to provide no stress or a tensile stress on a sidewall of the polysilicon structure,
the polysilicon structure having an upper surface and a lower surface, and the etching of the polysilicon layer being arranged to cause a width of the upper surface of the polysilicon structure to be greater than that of the lower surface of the polysilicon structure.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

13/314,462Filed 8 Dec 2011

Published

US 2013/0146993 A113 Jun 2013

Granted

5 Nov 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 64/01324
Characterised by the conductor: characterised by the sectional shape, e.g. T or inverted-T
H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 64/518
Characterised by the conducting layers: characterised by their lengths or sectional shapes

Semiconductor structure having a polysilicon structure and method of forming same

Life of this patent

Semiconductor structure having a polysilicon structure and method of forming same

Life of this patent

Abstract

Claims20