Integrating formation of a replacement gate transistor and a non-volatile memory cell using an interlayer dielectric

A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising:

• forming a first dielectric layer over a semiconductor layer in the NVM region and the logic region;
• forming a charge storage layer over the first dielectric layer in the NVM region and the logic region;
• patterning the charge storage layer to form a dummy gate in the logic region;
• patterning the charge storage layer to form a charge storage structure in the NVM region;
• forming a second dielectric layer over the semiconductor layer in the NVM region and the logic region, wherein the second dielectric layer surrounds the charge storage structure in the NVM region and the dummy gate in the logic region;
• using a replacement gate process to replace the dummy gate with a logic gate in the logic region;
• forming a hard mask layer over the logic gate and the second dielectric layer in the logic region;
• removing the second dielectric layer from the NVM region;
• forming a third dielectric layer over the semiconductor layer and charge storage structure in the NVM region and over the hard mask layer in the logic region;
• forming a control gate layer over the third dielectric layer in the NVM region and the logic region;
• and
• removing the hard mask layer, the third dielectric layer, and the control gate layer from the logic region.

A method for forming a semiconductor device having a non-volatile memory (NVM) region and a logic region, the method comprising:

• forming a first gate dielectric layer over a semiconductor layer in the NVM region and the logic region;
• forming a polysilicon layer over the first gate dielectric layer in the NVM region and the logic region;
• patterning the polysilicon layer to form a dummy gate in the logic region while protecting the NVM region;
• patterning the polysilicon layer to form a charge storage layer in the NVM region while protecting the logic region;
• forming an interlayer dielectric (ILD) layer in the NVM region and the logic region, wherein the ILD layer surrounds the charge storage layer in the NVM region and the dummy gate in the logic region, and a top surface of the ILD layer is substantially coplanar with top surfaces of the charge storage layer and the dummy gate;
• forming a sidewall spacer adjacent a sidewall of the dummy gate;
• forming source/drain regions in the semiconductor layer adjacent the dummy gate;
• replacing the dummy gate with a logic gate in the logic region;
• removing the ILD layer from the NVM region while protecting the ILD layer in the logic region;
• forming one or more dielectric layers over the semiconductor layer and charge storage layer in the NVM region;
• and
• forming a control gate layer over the one or more dielectric layers in the NVM region.