Implementing eDRAM stacked FET structure

A method for implementing an embedded dynamic random access memory (eDRAM) circuit comprising:

• forming a stacked structure including a field effect transistor (FET) and a capacitor;
• said capacitor being disposed above said FET in said stacked structure;
• and forming said stacked structure includes:
• depositing a first high-K dielectric material layer on a semiconductor substrate layer;
• depositing a first metal layer, depositing a second high-K dielectric material layer on the first metal layer;
• depositing a second metal layer, depositing a third high-K dielectric material layer on the second metal layer;
• and etching said first and second metal layers stack to define a gate stack of said FET of the eDRAM;
• depositing a silicon dioxide (SiO2) spacer film on said third high-K dielectric material layer of said gate stack;
• implanting source and drain regions in said semiconductor substrate layer adjacent said gate stack forming a source and drain of said FET;
• growing a first epitaxial (epi) silicon layer on said silicon dioxide (SiO2) spacer film on said third high-K dielectric material layer of said gate stack to define to source and drain (S/D) diffusions in said first epitaxial (epi) silicon layer and performing an oxygen implant step to separate said top source and drain (S/D) diffusions from said source and drain regions in said semiconductor layer.