Method for integrating silicon germanium and carbon doped silicon with source/drain regions in a strained CMOS process flow

A method for manufacturing a semiconductor device, including integrating silicon germanium and carbon doped silicon within source/drain regions in a CMOS process flow, comprising:

• providing a substrate having isolated PMOS and NMOS device regions;
• forming a first gate structure over an N-type well region in the substrate in the PMOS device region and a second gate structure over a P-type well region in the substrate in the NMOS device region, each gate structure comprising a polysilicon gate electrode overlying a gate dielectric, and a gate hardmask overlying the polysilicon gate electrode;
• forming gate sidewall spacers on opposite sides of the first and second gate structures;
• forming extension implants respectively within the N-type well region and the P-type well region;
• forming recesses within the N-type well region on opposing sides of the first gate structure;
• forming silicon germanium epitaxially within the recesses formed within the N-type well region on the opposing sides of the first gate structure;
• forming gate source/drain spacers over the gate sidewall spacers on opposite sides of the gate structures;
• forming source/drain implants respectively within the epitaxially formed silicon germanium in the N-type well region and within the P-type well region;
• performing at least one anneal to activate the extension implants and the source/drain implants;
• after performing the at least one anneal, forming recesses with the P-type well region on opposing sides of the second gate structure, including within portions of the activated source/drain implants within the P-type well region, leaving other portions of the activated source/drain implants within the P-type well region remaining;
• and
• forming carbon doped silicon epitaxially within the recesses formed within the P-type region on the opposing sides of the second gate structure, wherein the remaining other portions of the activated source/drain implants are not located within the epitaxially formed carbon doped silicon.

A method for manufacturing a semiconductor device, including integrating silicon germanium and carbon doped silicon within source/drain regions in a CMOS process flow, comprising:

• providing a substrate having isolated PMOS and NMOS device regions, a first gate structure formed over the substrate in the PMOS device region, a second gate structure formed over the substrate in the NMOS device region, and gate sidewall spacers formed on opposite sides of the first and second gate structures;
• with the gate sidewall spacers in place, selectively respectively forming P-type dopant extension implants in the PMOS device region and N type dopant extension implants in the NMOS device region;
• after forming the extension implants, selectively forming recesses in the PMOS device region on opposing sides of the first gate structure leaving at least part of the P-type dopant extension implants and all of the N-type dopant extension implants remaining;
• depositing silicon germanium in the recesses in the PMOS device region to form recessed epitaxial silicon germanium regions on the opposing sides of the first gate structure;
• after forming the recessed epitaxial silicon germanium regions, forming gate source/drain spacers over the gate sidewall spacers on opposite sides of the first and second gate structures;
• with the gate source/drain spacers in place, selectively respectively forming P-type dopant source/drain implants in the recessed epitaxial silicon germanium regions in the PMOS device region and N-type dopant source/drain implants in the substrate in the NMOS device region;
• after forming the source/drain implants, performing at least one anneal greater than about 800° C. to activate the remaining part of the P-type extension implants, the P-type source/drain implants, the N-type extension implants and the N-type source/drain implants;
• after performing the at least one anneal, selectively forming recesses on opposing sides of the second gate structure in the NMOS device region, including in portions of the activated N-type source/drain implants, leaving other portions of the activated N-type source/drain implants remaining;
• and
• depositing carbon doped silicon in the recesses in the NMOS device region to form recessed epitaxial carbon doped silicon regions on the opposing sides of the second gate structure, wherein the activated N-type extension implants and remaining other portions of the activated N-type source/drain implants are not located within the epitaxial carbon doped silicon regions.

A method for manufacturing a semiconductor device, comprising:

• providing a substrate including a PMOS device region and an NMOS device region;
• forming a first gate structure, including a first gate dielectric, a first gate electrode and first gate sidewall spacers, over the substrate in the PMOS device region;
• forming recessed epitaxial SiGe regions in the substrate on opposing sides of the first gate structure and offset by a second distance d1 from sidewalls of the first gate electrode using the first gate sidewall spacers;
• forming first source/drain spacers over the first gate sidewall spacers after forming the recessed epitaxial SiGe regions;
• forming first source/drain regions on opposing sides of the first gate structure using the first gate sidewall spacers, and first source/drain spacers, at least a portion of each first source/drain region being located within at least a portion of a corresponding one of the recessed epitaxial SiGe regions;
• forming a second gate structure, including a second gate dielectric, a second gate electrode, second gate sidewall spacers and second source/drain spacers, over the substrate in the NMOS device region;
• forming second source/drain regions on opposing sides of the second gate structure using the second gate sidewall spacers and first source/drain spacers;
• activating the first source/drain regions and second source/drain regions using a thermal anneal at a temperature of greater than 800° C.;
• and
• following the thermal anneal, forming recessed epitaxial SiC regions in the substrate on opposing sides of the second gate structure and offset by a second distance d2 from sidewalls of the second gate electrode using the second gate sidewall spacers and the second source/drain spacers, wherein the recessed epitaxial SiC regions replace portions of the activated second source/drain regions, and wherein other portions of the activated second source/drain regions remain which are not located within the recessed epitaxial SiC regions.