# US 8,572,619 B2 · System and method for integrating software schedulers and hardware interrupts for a deterministic system

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- Number: US 8,572,619 B2
- Document ID: US8572619B2
- Status: Granted
- Kind: B2
- Application number: 12/931,262
- Filed: 2011-01-27
- Published: 2011-07-28
- Granted: 2013-10-29
- Earliest claimed: 2010-01-28
- Assignees: Real Time, Inc.
- Applicants: Victor Webber
- Inventors: Victor Webber
- Web page: https://patentgrep.com/patent/US8572619B2

## CPC

- G06F 9/4887: {involving deadlines, e.g. rate based, periodic}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

The problem which is being addressed by this invention is the lack of determinism in mass market operating systems. This invention provides a mechanism for mass market operating systems running on mass market hardware to be extended to create a true deterministic responsive environment. This is accomplished through programming hardware elements of the scheduler to behave deterministically with respect to the software scheduler.

## Claims

### Claim 1

A computerized method to incorporate interrupts in a stable task set for tasks scheduling comprising:
creating a plurality of stable task sets, each of the plurality of stable task sets comprising tasks having a same priority level set and each of the tasks having a time period for executing by a processor; Wherein the tasks in the stable task set including one or more of at least one of aperiodic tasks, periodic tasks and interrupts;
wherein tasks registered to one of the stable task sets complete their respective executions within the time period allotted to that stable task set, and the tasks must register their respective resource usage requirements, within their respective periods of execution, and deregister their resource requirements when they are no longer needed; wherein interrupts register their worst case resource requirements and the interrupts are initially unmasked in anticipation of an initial interrupt;
executing all scheduled tasks in one of the stable task set during the time period allocated for executing of the stable task set;
determining that together the all scheduled tasks in the one of the stable task set consume less than a total resources of the processor; and
determining a constant value associated with resources overhead used due to context switching between the tasks or instructions that enabling or disabling interrupts during the time period of execution of the stable task set, wherein the interrupts using the worst case resource requirements;
checking whether the consume resources and the constant value are less than or equal to the total resources of the processor; and
scheduling one of the stable task set having a highest priority among the plurality of stable task and having the checking step result that the consume resources and the constant value are less than or equal to the total resources of the processor.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plurality of the stable task sets include cascaded priority stable task sets integrate an activity of a lower priority level tasks into a next higher priority level task.