US 8,572,546 B2Granted

Methods of modeling a transistor and apparatus used therein

AssigneeElectronics and Telecommunications Research Institute

InventorsJaeheon Shin, Woo-Seok Cheong, Chi-Sun Hwang, Sung Mook Chung

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Abstract

Methods of modeling a transistor are provided. The method includes the steps of (a) extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage, (b) fitting a mobility function including model parameters on the reference mobility values to extract the model parameters, and (c) putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region. Related apparatuses are also provided.

Claims15

Dependent claims

A method of modeling a transistor, the method comprising performing, by an apparatus including a memory unit, the steps of:

extracting reference mobility values of a channel layer of a transistor including a gate electrode, a source region and a drain region using a reference gate voltage, a reference drain current and a reference drain voltage;
fitting a mobility function including model parameters on the reference mobility values to extract the model parameters;
and
putting the extracted model parameters into a drain current modeling function to calculate a drain current flowing through the channel layer between the drain region and the source region under a bias condition defined by an arbitrary gate voltage applied to the gate electrode and an arbitrary drain voltage applied to the drain region;
wherein the mobility function is expressed by the following equation,
μ
=
(
1
K
b
⁡
(
V
gate
-
V
on
)
β
+
1
K
a
⁡
(
V
gate
-
V
on
)
α
)
-
1
wherein, “Ka”, “Kb”, “α” and “β” denote the model parameters, “Vgate” denotes the reference gate voltage applied to the gate electrode, “Von” denotes a turn on voltage of the transistor, and “μ” denotes a mobility of the channel layer calculated using the model parameters, the reference gate voltage and the turn on voltage.

34 more elements

An apparatus used in modeling a transistor, the apparatus comprising:

a reference mobility extraction unit for extracting reference mobility values of a channel layer of the transistor including a gate electrode, a source region and a drain region using a reference gate voltage applied to the gate electrode and a reference drain current flowing through the channel layer in response to the reference gate voltage;
a fitting unit for extracting model parameters by fitting a mobility function of the model parameters on the reference mobility values;
and
a drain current modeling unit for calculating a drain current flowing through the channel layer by putting an arbitrary gate voltage applied to the gate electrode, an arbitrary drain voltage applied to the drain region and the model parameters into a drain current modeling function;
wherein the drain current modeling unit additionally puts a channel length of the transistor, a channel width of the transistor, a gate capacitance between the channel layer and the gate electrode, an arbitrary drain voltage applied to the drain region, and a turn on voltage of the transistor into the drain current modeling function,
wherein the fitting unit extracts the model parameters by fitting a mobility function on the reference mobility values,
wherein the mobility function is expressed by the following equation,
μ
=
(
1
K
b
⁡
(
V
gate
-
V
on
)
β
+
1
K
a
⁡
(
V
gate
-
V
on
)
α
)
-
1
wherein, “Ka”, “Kb”, “α” and “β” denote the model parameters, “Vgate” denotes the reference gate voltage corresponding to a gate voltage applied to the gate electrode, “Von” denotes a turn on voltage of the transistor, and “μ” denotes a mobility of the channel layer that is calculated using the model parameters, the reference gate voltage and the turn on voltage, and
wherein the drain current modeling function is expressed by the following equation,
I
d
=
CW
L
⁢
∫
0
V
d
⁢
(
1
K
b
⁡
(
V
g
-
V
on
-
V
y
)
β
+
1
K
a
⁡
(
V
g
-
V
on
-
V
y
)
α
)
-
1
×
(
V
g
-
V
on
-
V
y
)
⁢
ⅆ
V
y
wherein, “Id” denotes the drain current, “Vg” denotes the arbitrary gate voltage, “Vd” denotes the arbitrary drain voltage, “L” denotes a channel length of the transistor, “W” denotes a channel width of the transistor, “C” denotes a gate capacitance between the channel layer and the gate electrode, and “Von” denotes the turn on voltage of the transistor.

99 more elements

Dependencies are inferred from the claim text.