Programmatic auto-convergent method for “physical layout power hot-spot” risk aware ASIP architecture customization for performance optimization

A method to manage power in a custom integrated circuit (IC) design, comprising:

• receiving a specification of the custom integrated circuit including computer readable code and generating a profile of the computer readable code to determine instruction usage;
• automatically generating an application specific instruction set processor architecture uniquely customized to the computer readable code with a compiler-in-the-loop to compile, assemble and link code for each processor architecture iteration, the processor architecture having one or more processing blocks on the IC executing one or more instructions;
• determining an instruction execution sequence based on the code profile and spatially assigning the processing blocks to spread operations or activities to different areas on the IC to reduce hot spots;
• wherein the instruction contain instruction scheduler to made aware of power usage through the data model and see the true cost of scheduling instruction execution to get high performance with minimal hot spots on the chip;
• wherein the instruction scheduler is power aware in that the instruction scheduler use predicted hot spot information and map this information to virtual resource constraints so that standard off-the-shelf instruction scheduler can become power aware;
• wherein a data model associates an instruction's steady state probability of execution to a topology of an execution path;
• and
• synthesizing the generated architecture into a computer readable description of the custom integrated circuit for semiconductor fabrication.