# US 8,572,543 B2 · Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,543 B2 - Document ID: US8572543B2 - Status: Granted - Kind: B2 - Application number: 13/442,099 - Filed: 2012-04-09 - Published: 2012-08-02 - Granted: 2013-10-29 - Earliest claimed: 2005-12-19 - Assignees: LSI Corporation - Applicants: Juergen Dirks; Matthias Dinter; Ralf Leuchter - Inventors: Juergen Dirks; Matthias Dinter; Ralf Leuchter - Web page: https://patentgrep.com/patent/US8572543B2 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles. ## Claims ### Claim 1 A method of designing an integrated circuit, comprising the steps of: (A) generating a design layout of said integrated circuit in a computer, said design layout comprising (i) a plurality of common cells each configured to perform a logical operation and (ii) a logic gate having a logic input fixed to a logic level; (B) replacing at least one of said common cells proximate said logic gate with a special cell configured to (i) perform said logical operation and (ii) generate a signal at said logic level; (C) removing a connection that fixes said logic input of said logic gate to said logic level; (D) routing said signal from said special cell to said logic input of said logic gate, wherein (i) said logic gate resides inside a first of a plurality of boundaries in said design layout, (ii) said design layout further comprises a scan chain having a scan cell within said first boundary, (iii) an additional logic gate resides in a second of said boundaries and (iv) said second boundary adjoins said first boundary; and (E) marking said second boundary as full in response to said second boundary lacking available space to place another scan cell. ### Claim 2 (depends on 1) The method according to claim 1, wherein said logical operation comprises a flip-flop operation. ### Claim 3 (depends on 1) The method according to claim 1, wherein said special cell is configured to generate said signal at a logical high level. ### Claim 4 (depends on 1) The method according to claim 1, wherein said special cell is configured to generate said signal at a logical low level. ### Claim 5 (depends on 1) The method according to claim 1, wherein said design layout further comprises another logic gate having another logic input fixed to said logic level, the method further comprising the steps of: removing another connection that fixes said other logic input of said other logic gate to said logic level; and routing said signal from said special cell to said other logic input of said other logic gate. ### Claim 6 (depends on 1) The method according to claim 1, wherein said design layout further comprises another logic gate having another logic input fixed to said logic level, the method further comprising the steps of: adding a tie-to cell to said design layout proximate said other logic gate, wherein said tie-to cell is configured to generate another signal at said logic level; removing another connection that fixes said other logic input of said other logic gate to said logic level; and routing said other signal from said tie-to cell to said other logic input of said other logic gate. ### Claim 7 (depends on 1) The method according to claim 1, wherein (i) said special cell comprises a given scan cell and (ii) said design layout further comprises another logic gate having another logic input fixed to a particular logic level. ### Claim 8 (depends on 7) The method according to claim 7, further comprising the steps of: removing another connection that fixes said other logic input of said other logic gate to said particular logic level; and routing a data output of said given scan cell to said other logic input of said other logic gate. ### Claim 9 (depends on 7) The method according to claim 7, further comprising the step of: routing a data output of said given scan cell to another scan cell in said design layout. ### Claim 10 (depends on 1) The method according to claim 1, further comprising the steps of: rerouting said logic input of said logic gate to a data output of said scan cell. ### Claim 11 (depends on 1) The method according to claim 1, wherein the steps are preformed by processor executable instructions contained within a non-transitory computer readable medium. ### Claim 12 A method of designing an integrated circuit, comprising the steps of: (A) generating a design layout of said integrated circuit in a computer, said design layout comprising (i) a scan chain and (ii) a plurality of logic gates, at least one of said logic gates having a logic input fixed to a logic level and residing inside a first of a plurality of boundaries in said design layout; (B) adding a scan cell within said first boundary; (C) rerouting said logic input of said at least one logic gate to a data output of said scan cell; and (D) rerouting said scan chain to include said scan cell. ### Claim 13 (depends on 12) The method according to claim 12, wherein (i) another of said logic gates resides in a second of said boundaries and (ii) said second boundary adjoins said first boundary, the method further comprising the step of: marking said second boundary as full in response to said second boundary lacking available space to place another scan cell. ### Claim 14 (depends on 12) The method according to claim 12, further comprising the step of: adding another scan cell within said first boundary in response to a second boundary being marked as full. ### Claim 15 (depends on 14) The method according to claim 14, further comprising the step of: rerouting another logic input of another cell in said second boundary to a data output of said other scan cell. ### Claim 16 (depends on 12) The method according to claim 12, wherein said design layout further comprises (i) a plurality of common cells each configured to perform a logical operation and (ii) another of said logic gates having another logic input fixed to said logic level. ### Claim 17 (depends on 16) The method according to claim 16, further comprising the steps of: replacing at least one of said common cells proximate said other logic gate with a special cell configured to (i) perform said logical operation and (ii) generate a signal at said logic level; removing a connection that fixes said other logic input of said other logic gate to said logic level; and routing said signal from said special cell to said other logic input of said other logic gate. ### Claim 18 (depends on 16) The method according to claim 16, wherein said logical operation comprises a flip-flop operation. ### Claim 19 (depends on 12) The method according to claim 12, wherein the steps are preformed by processor executable instructions contained within a non-transitory computer readable medium.