# US 8,572,537 B2 · Accurate parasitic capacitance extraction for ultra large scale integrated circuits

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- Number: US 8,572,537 B2
- Document ID: US8572537B2
- Status: Granted
- Kind: B2
- Application number: 13/527,096
- Filed: 2012-06-19
- Published: 2012-10-11
- Granted: 2013-10-29
- Earliest claimed: 2007-06-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Ke-Ying Su; Chia-Ming Ho; Gwan-Sin Chang; Chien-Wen Chen
- Inventors: Ke-Ying Su; Chia-Ming Ho; Gwan-Sin Chang; Chien-Wen Chen
- Web page: https://patentgrep.com/patent/US8572537B2

## CPC

- G01R 31/2853: {Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections (G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66)}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- G01R 31/2884: {using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence)}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A system and method for extracting the parasitic contact/via capacitance in an integrated circuit are provided. Parasitic extraction using this system can lead to an improved accuracy on contact/via parasitic capacitance extraction by taking into account of the actual contact/via shape and size variation. The common feature of the various embodiments includes the step of generating a technology file, in which the contact/via capacitance in the capacitance table is derived from an effective contact/via width table. Each element of the effective contact/via width table is calibrated to have a parasitic capacitance matching to that of an actual contact/via configuration occurring in an IC.

## Claims

### Claim 1

A method comprising:
reading a technology file into an extraction system; and
reading a circuit layout into said extraction system;
wherein said technology file includes a capacitance table;
wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and
wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof.

### Claim 2 (depends on 1)

The method of claim 1, wherein said each element of said effective connector table has a polygon-shaped connector.

### Claim 3 (depends on 2)

The method of claim 2, wherein said each element in said effective connector area table is represented by a width of a square-shaped connector.

### Claim 4 (depends on 1)

The method of claim 1, wherein said effective connector area table includes an effective via area table corresponding to vias between two different interconnect layers in said IC.

### Claim 5 (depends on 1)

The method of claim 1 further comprising pattern-matching a geometry of said circuit layout to a corresponding element of said capacitance table.

### Claim 6 (depends on 5)

The method of claim 5 further comprising retrieving said element of said capacitance table.

### Claim 7 (depends on 1)

The method of claim 1 further comprising forming said actual connector configuration in a semiconductor substrate.

### Claim 8

A method comprising:
reading a technology file into an extraction system;
reading a circuit layout into said extraction system;
processing a geometry of said circuit layout in said extraction system; and
using said extraction system, extracting parasitic capacitance by pattern-matching a connector configuration in said technology file to a pattern in said circuit layout;
wherein said technology file includes a capacitance table;
wherein a connector capacitance in said capacitance table is derived from an effective connector area table; and
wherein each element of said effective connector area table is calibrated to have a parasitic capacitance value matching with a measured parasitic capacitance of an actual connector configuration in an integrated circuit (IC), said actual connector configuration including a via, a contact, or a combination thereof.

### Claim 9 (depends on 8)

The method of claim 8 further comprising creating said technology file including:
providing connector capacitance test structures having substantially similar dimensions and different connector configurations;
measuring a parasitic connector capacitance on each of said connector capacitance test structures;
creating an effective connector width table, wherein each element of said effective connector width table corresponds to a polygon-shaped connector and has a calculated parasitic capacitance matching to a measured parasitic capacitance of one of said connector capacitance test structures; and
generating a capacitance table corresponding to said effective connector width table.

### Claim 10 (depends on 9)

The method of claim 9, wherein said creating said effective connector width table includes:
providing said measured parasitic capacitance;
preparing a process characterization file, said process characterization file including a trial value of a connector area;
calculating a connector parasitic capacitance value by using a field solver with said process characterization file; and
comparing the calculated connector parasitic capacitance value with the measured parasitic capacitance to determine an effective connector width.

### Claim 11 (depends on 8)

The method of claim 8, further comprising extracting parasitic capacitance by interpolating or extrapolating capacitance values in said capacitance table of said technology file.

### Claim 12 (depends on 8)

The method of claim 8 further comprising outputting a parasitic extraction result in a netlist of RC values.

### Claim 13 (depends on 8)

The method of claim 8 further comprising performing a simulation based on said circuit layout using said extracted parasitic capacitance.

### Claim 14 (depends on 13)

The method of claim 13 further comprising optimizing said circuit layout based on said performing said simulation.

### Claim 15 (depends on 13)

The method of claim 13, wherein said actual connector configuration in said IC includes vias in a first dielectric layer over and adjoining a semiconductor substrate and/or includes contacts in a second dielectric layer over and adjoining said first dielectric layer.

### Claim 16 (depends on 13)

The method of claim 13 further comprising forming said actual connector configuration in a semiconductor substrate.

### Claim 17 (depends on 8)

The method of claim 8, wherein said each element of said effective connector table has a polygon-shaped connector.

### Claim 18 (depends on 17)

The method of claim 17, wherein said each element in said effective connector area table is represented by a width of a square-shaped connector.

### Claim 19 (depends on 8)

The method of claim 8, wherein said effective connector area table includes an effective via area table corresponding to vias between two different interconnect layers in said IC.

### Claim 20 (depends on 8)

The method of claim 8 further comprising retrieving said connector configuration of said capacitance table.