# US 8,572,530 B1 · Method and apparatus for performing path-level skew optimization and analysis for a logic design > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,530 B1 - Document ID: US8572530B1 - Status: Granted - Kind: B1 - Application number: 12/928,245 - Filed: 2010-12-06 - Granted: 2013-10-29 - Earliest claimed: 2005-11-04 - Assignees: Altera Corporation - Applicants: Ryan Fung; Vaughn Betz; David Karchmer - Inventors: Ryan Fung; Vaughn Betz; David Karchmer - Web page: https://patentgrep.com/patent/US8572530B1 ## CPC - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 1/10: Distribution of clock signals {, e.g. skew} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed. ## Claims ### Claim 1 A method for evaluating a system, comprising: computing a path-level deviation from a skew schedule in the system by determining a maximum path delay and a minimum path delay for a skew domain with a timing graph modified in response to a skew schedule, and computing a difference between the maximum path delay and the minimum path delay for the skew domain, wherein the skew schedule specifies a relationship between path delays to achieve a particular skew between the path delays; and analyzing the path-level deviation from the skew schedule in the system by determining whether the path-level deviation from the skew schedule satisfies a skew constraint, wherein one of the computing and analyzing is performed by a processor. ### Claim 2 (depends on 1) The method of claim 1, wherein the analyzing further comprises: comparing the path-level deviation from the skew schedule with a maximum tolerable skew for a skew domain to determine slack. ### Claim 3 (depends on 1) The method of claim 1, wherein the analyzing further comprises: determining whether the skew schedule associated with a path-level skew is satisfied. ### Claim 4 (depends on 1) The method of claim 1, wherein the analyzing further comprises: comparing the path-level deviation from the skew schedule with a maximum tolerable deviation from the skew schedule for a skew domain to determine slack. ### Claim 5 (depends on 1) The method of claim 1, further comprising reporting results of the analysis. ### Claim 6 (depends on 1) The method of claim 1, further comprising optimizing the path-level deviation from a skew schedule in the system by generating connection-level long-path and short-path skew slacks for one or more skew domains given a tolerable deviation from the skew schedule for each skew domain in response to the analyzing. ### Claim 7 (depends on 1) The method of claim 1, further comprising: prior to the analyzing, synthesizing the system on a target device; prior to the analyzing, placing the system on the target device; prior to the analyzing, routing the system on the target device; and in response to the analyzing, modifying a result of one of the synthesizing, placing, and routing procedures. ### Claim 8 A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method comprising: computing a path-level deviation from a skew schedule in the system by determining a maximum path delay and a minimum path delay for a skew domain with a timing graph modified in response to a skew schedule, and computing a difference between the maximum path delay and the minimum path delay for the skew domain; and analyzing the path-level deviation from the skew schedule in a system by determining whether the path-level deviation from the skew schedule satisfies a skew constraint. ### Claim 9 (depends on 8) The non-transitory computer readable medium of claim 8, wherein the method further comprises: prior to the analyzing, synthesizing the system on a target device; prior to the analyzing, placing the system on the target device; prior to the analyzing, routing the system on the target device; and in response to the analyzing, modifying a result of one of the synthesizing, placing, and routing procedures. ### Claim 10 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the method further comprises: re-analyzing the path-level skew in the system in response to the modifying. ### Claim 11 (depends on 8) The non-transitory computer readable medium of claim 8, wherein the method further comprises: performing one of synthesis, placement, and routing of the system in response to the analyzing. ### Claim 12 (depends on 8) The non-transitory computer readable medium of claim 8, wherein the method further comprises: reporting results of the analysis. ### Claim 13 (depends on 8) The non-transitory computer readable medium of claim 8, wherein the analyzing further comprises: determining whether the skew schedule is satisfied. ### Claim 14 (depends on 8) The non-transitory computer readable medium of claim 8, wherein the method further comprises: optimizing the path-level deviation from a skew schedule in the system by generating connection-level long-path and short-path skew slacks for one or more skew domains given a tolerable deviation from the skew schedule for each skew domain in response to the analyzing. ### Claim 15 A system designer, comprising: a path-level skew optimization unit that includes a delay estimation unit operable to determine a maximum path delay and minimum path delay for a skew domain in a system with a timing graph modified in response to a skew schedule, and a timing analysis unit operable to compute a difference between the maximum path delay and minimum path delay for the skew domain to determine a path-level deviation from the skew schedule in the system, and operable to analyze the path-level deviation from the skew schedule in the system by determining whether the path-level deviation from the skew schedule satisfies a skew constraint, wherein the path-level skew optimization unit is implemented in hardware. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the path-level skew optimization unit is operable to generate a report of the analysis performed. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the report is rendered to a designer. ### Claim 18 (depends on 15) The apparatus of claim 15, further comprising: a synthesis unit operable to synthesize the system on a target device prior to the analyzing; a placement unit operable to place the system on the target device prior to the analyzing; and a routing unit operable to route the system prior to the analyzing, wherein at least one of the synthesis unit, placement unit, and routing unit is operable to modify a result in response to the analysis performed by the path-level skew optimization unit. ### Claim 19 (depends on 15) The apparatus of claim 15, wherein the path-level skew optimization unit determines whether the path-level deviation from the skew schedule satisfies a skew constraint. ### Claim 20 A method for evaluating a system, comprising: computing a path-level deviation from a skew schedule in the system by determining a maximum path delay and a minimum path delay for a skew domain with a timing graph modified in response to a skew schedule, and computing a difference between the maximum path delay and the minimum path delay for the skew domain, wherein the skew schedule specifies a relationship between path delays to achieve a particular skew between the path delays; routing the system on a target device; and analyzing the path-level deviation from the skew schedule in the system after routing the system by determining whether the path-level deviation from the skew schedule satisfies a skew constraint, wherein one of the computing, routing, and analyzing is performed by a processor. ### Claim 21 (depends on 20) The method of claim 20, further comprising: prior to the analyzing, synthesizing the system on the target device; prior to the analyzing, placing the system on the target device; and in response to the analyzing, modifying a result of one of the synthesizing, placing, and routing procedures.