# US 8,572,528 B1 · Method and apparatus for analyzing a design of an integrated circuit using fault costs > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,528 B1 - Document ID: US8572528B1 - Status: Granted - Kind: B1 - Application number: 12/626,559 - Filed: 2009-11-25 - Granted: 2013-10-29 - Earliest claimed: 2009-11-25 - Assignees: Xilinx, Inc. - Applicants: William E. Leigh; Kenneth R. Weidele - Inventors: William E. Leigh; Kenneth R. Weidele - Web page: https://patentgrep.com/patent/US8572528B1 ## CPC - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/3323: using formal methods, e.g. equivalence checking or property checking - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In one embodiment, a method and apparatus for analyzing a design of an integrated circuit (IC) are disclosed. For example, the method parses a netlist file of the IC where a module of the IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure. The method traces through a connectivity of the plurality of sub-modules, and tabulates data associated with the connectivity with a fault cost associated with a structure of the IC. ## Claims ### Claim 1 A method for analyzing a design of an integrated circuit (IC), comprising: assigning a fault cost to a plurality of endpoint structures of the IC; parsing a netlist file of said IC where a module of said IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure until the plurality of endpoint structures of the IC is reached; tracing through an end-to-end connectivity of said plurality of sub-modules to produce an overall connectivity map for the IC, wherein said tracing comprises mapping each input signal and output signal of the module through the plurality of sub-modules to the plurality of endpoint structures; and tabulating data associated with the end-to-end connectivity with the fault cost assigned to at least one of the plurality of endpoint structures of the IC. ### Claim 2 (depends on 1) The method of claim 1, further comprising: generating said netlist file in a text-based format. ### Claim 3 (depends on 1) The method of claim 1, wherein said parsing comprises: organizing said IC or a portion of said IC into said plurality of sub-modules. ### Claim 4 (depends on 3) The method of claim 3, wherein said organizing comprises: organizing a configurable logic block (CLB) of said IC into said plurality of sub-modules. ### Claim 5 (depends on 1) The method of claim 1, wherein said parsing comprises: generating a plurality of levels of said hierarchical structure in order from a highest level of said hierarchical structure to a lowest level of said hierarchical structure. ### Claim 6 (depends on 5) The method of claim 5, wherein said parsing further comprises: representing said IC in the highest level of said hierarchical structure. ### Claim 7 (depends on 5) The method of claim 5, wherein said parsing further comprises: representing one or more transistors in the lowest level of said hierarchical structure. ### Claim 8 (depends on 5) The method of claim 5, wherein said tracing comprises, at each of the plurality of levels: tracking a total number of the plurality of sub-modules that is instantiated at a next lower level of the plurality of levels. ### Claim 9 (depends on 1) The method of claim 1, wherein said assigning comprises: expressing said fault cost in terms of a number of transistors in said module that needs to fail. ### Claim 10 (depends on 1) The method of claim 1, further comprising: applying said fault cost in a fault isolation analysis. ### Claim 11 (depends on 1) The method of claim 1, wherein the parsing comprises: determining a name for the module; determining a list containing the each input signal and output signal of the module; and determining the plurality of sub-modules. ### Claim 12 (depends on 1) The method of claim 1, wherein said tracing comprises: matching a direction specifier to the each input signal and output signal of the module; and matching names of nets of the module to names of input signals and output signals of the plurality of sub-modules. ### Claim 13 (depends on 1) The method of claim 1, wherein the tracing comprises: marking each of the plurality of endpoint structures as an end node of a complete path through said plurality of sub-modules. ### Claim 14 A computer-readable storage medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to perform steps of a method for analyzing a design of an integrated circuit (IC), comprising: assigning a fault cost to a plurality of endpoint structures of the IC; parsing a netlist file of said IC where a module of said IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure until the plurality of endpoint structures of the IC is reached; tracing through an end-to-end connectivity of said plurality of sub-modules to produce an overall connectivity map for the IC, wherein said tracing comprises mapping each input signal and output signal of the module through the plurality of sub-modules to the plurality of endpoint structures; and tabulating data associated with the end-to-end connectivity with the fault cost assigned to at least one of the plurality of endpoint structures of the IC. ### Claim 15 (depends on 14) The computer-readable storage medium of claim 14, further comprising: generating said netlist file in a text-based format. ### Claim 16 (depends on 14) The computer-readable storage medium of claim 14, wherein said parsing comprises: organizing said IC or a portion of said IC into said plurality of sub-modules. ### Claim 17 (depends on 14) The computer-readable storage medium of claim 14, wherein said parsing comprises: generating a plurality of levels of said hierarchical structure in order from a highest level of said hierarchical structure to a lowest level of said hierarchical structure. ### Claim 18 (depends on 17) The computer-readable storage medium of claim 17, wherein said parsing further comprises: representing said IC in the highest level of said hierarchical structure; and representing one or more transistors in the lowest level of said hierarchical structure. ### Claim 19 (depends on 14) The computer-readable storage medium of claim 14, wherein said assigning comprises: expressing said fault cost in terms of a number of transistors in said module that needs to fail. ### Claim 20 An apparatus for analyzing a design of an integrated circuit (IC), comprising: a processor executing a process that performs: assigning a fault cost to a plurality of endpoint structures of the IC; parsing a netlist file of said IC where a module of said IC is parsed into a plurality of sub-modules in accordance with a hierarchical structure until the plurality of endpoint structures of the IC is reached; tracing through an end-to-end connectivity of said plurality of sub-modules to produce an overall connectivity map for the IC that maps each input signal and output signal of the module through the plurality of sub-modules to the plurality of endpoint structures; and tabulating data associated with the end-to-end connectivity with the fault cost assigned to at least one of the plurality of endpoint structures of the IC.