Lithography aware leakage analysis

A computer program product stored on a non-transitory computer readable medium for performing leakage calculations, the computer program product comprising:

• code for receiving information specifying an integrated circuit;
• code for determining a neighborhood of shapes associated with the integrated circuit, wherein the code for determining the neighborhood of shapes comprises:
• code for determining a first set of spacings between a boundary of an internal shape of a first cell and a boundary of the first cell,
• code for determining a second set of spacings between the boundary of the first cell and a boundary of a shape of a second cell, and
• code for characterizing a lithography process using the first and second set of spacings;
• and
• code for generating leakage information associated with the integrated circuit based on calculating leakage in the integrated circuit using a simulation of the characterized lithography process.

A system for performing leakage calculations, the system comprising:

• a processor;
• and
• a memory coupled to the processor, the memory configured to store a set of instructions which when executed by the processor cause the processor to:
• receive information specifying an integrated circuit;
• determine a neighborhood of shapes associated with the integrated circuit wherein determining the neighborhood of shapes comprises:
• determining a first set of spacings between a boundary of an internal shape of a first cell and a boundary of the first cell,
• determining a second set of spacings between the boundary of the first cell and a boundary of a shape of a second cell, and
• characterizing a lithography process using the first and second set of spacings;
• and
• generate leakage information associated with the integrated circuit based on calculating leakage in the integrated circuit using a simulation of the characterized lithography process.

A method for determining circuit performance, the method comprising:

• receiving, at one or more computer systems, information specifying an integrated circuit;
• determining, with one or more processors associated with the one or more computer systems, a neighborhood of shapes of a plurality of cells associated with the integrated circuit, wherein determining the neighborhood of shapes comprises:
• determining a first set of spacings between a boundary of an internal shape associated with a first cell in the plurality of cells and a boundary of the first cell,
• determining a second set of spacings between the boundary of the first cell and a boundary of a shape associated with a second cell in the plurality of cells, and
• characterizing a lithography process using the first and second set of spacings;
• generating a mapping between the first and second set of spacings and leakage;
• calculating leakage of the first and second cells using a simulation of the characterized lithography process based on the first and second set of spacings;
• generating a mapping from the first and second set of spacings to delay;
• calculating delay of the first and second cells using a simulation of the characterized lithography process based on the first and second set of spacings;
• and
• generating, with the one or more processors associated with the one or more computer systems, performance information associated with the integrated circuit based on electrical connections between the first cell and the second cell in response to the calculated delays and leakages of the first and second cells.

A computer program product stored on a non-transitory computer readable medium for determining circuit performance, the computer program product comprising:

• code for receiving information specifying an integrated circuit;
• code for determining a neighborhood of shapes of a plurality of cells associated with the integrated circuit, wherein determining the neighborhood of shapes comprises:
• code for determining a first set of spacings between a boundary of an internal shape associated with a first cell in the plurality of cells and a boundary of the first cell,
• code for determining a second set of spacings between the boundary of the first cell and a boundary of a shape associated with a second cell in the plurality of cells, and
• code for characterizing a lithography process using the first and second set of spacings;
• code for generating a mapping between the first and second set of spacings and leakage;
• code for calculating leakage of the first and second cells using a simulation of the characterized lithography process based on the first and second set of spacings;
• code for generating a mapping from the first and second set of spacings to delay;
• code for calculating delay of the first and second cells using a simulation of the characterized lithography process based on the first and second set of spacings;
• and
• code for generating performance information associated with the integrated circuit based on electrical connections between the first and second cells in response to the calculated delays and leakages of the first and second cells.