# US 8,572,455 B2 · Systems and methods to respond to error detection > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,455 B2 - Document ID: US8572455B2 - Status: Granted - Kind: B2 - Application number: 12/546,095 - Filed: 2009-08-24 - Published: 2011-02-24 - Granted: 2013-10-29 - Earliest claimed: 2009-08-24 - Assignees: International Business Machines Corporation - Applicants: H. Lee Blackmon; Ryan S. Haraden; Joseph A. Kirscht; Elizabeth A. McGlone - Inventors: H. Lee Blackmon; Ryan S. Haraden; Joseph A. Kirscht; Elizabeth A. McGlone - Web page: https://patentgrep.com/patent/US8572455B2 ## CPC - G06F 11/141: {for bus or memory accesses} - G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)} - G06F 11/1666: {where the redundant component is memory or memory area} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port. ## Claims ### Claim 1 A method of responding to error detection, the method comprising: receiving first data at a first memory controller port in response to a first read command issued from the first memory controller port; issuing a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error; receiving second data at the second memory controller port in response to the second read command; and issuing a repair write command from the first memory controller port after determining that the second data does not contain any errors, wherein the repair write command initiates writing the second data from the first memory controller port. ### Claim 2 (depends on 1) The method of claim 1, further comprising issuing a confirmation read command from the first memory controller port after the repair write command is issued from the first memory controller port. ### Claim 3 (depends on 2) The method of claim 2, further comprising receiving third data in response to the confirmation read command issued from the first memory controller port. ### Claim 4 (depends on 3) The method of claim 3, further comprising invoking redundant bit steering to correct the third data in response to detecting that the third data has a single bit error. ### Claim 5 (depends on 3) The method of claim 3, further comprising issuing a subsequent read command from at least one of the first memory controller port and the second memory controller port after determining that the third data does not contain any errors. ### Claim 6 (depends on 1) The method of claim 1, further comprising directing a subsequent read command to issue from the second memory controller port in response to determining that the first data contains the uncorrectable error. ### Claim 7 (depends on 1) The method of claim 1, wherein the first memory controller port is connected to a first memory structure and the second memory controller port is connected to a second memory structure. ### Claim 8 (depends on 7) The method of claim 7, wherein the second memory structure is configured to mirror the first memory structure. ### Claim 9 (depends on 8) The method of claim 8, further comprising issuing a hot memory replace of the first memory structure with data from the second memory structure after determining that third data contains a second uncorrectable error. ### Claim 10 A method of responding to error detection, the method comprising: receiving first data at a first memory controller port in response to a read command sent from the first memory controller port; reissuing the read command as a second read command from the first memory controller port after determining that the first data contains an uncorrectable error; receiving second data at the first memory controller port in response to the second read command; issuing a third read command from a second memory controller port after determining that the second data contains a second uncorrectable error; and receiving third data at the second memory controller port in response to the third read command. ### Claim 11 (depends on 10) The method of claim 10, further comprising reissuing the third read command as a fourth read command from the second memory controller port after determining that the third data contains a third uncorrectable error. ### Claim 12 (depends on 11) The method of claim 11, wherein the fourth read command includes an uncorrectable error retry read command. ### Claim 13 (depends on 12) The method of claim 12, further comprising receiving fourth data at the second memory controller port in response to the fourth read command. ### Claim 14 (depends on 13) The method of claim 13, further comprising issuing a machine check condition to a source after determining that the fourth data contains a fourth uncorrectable error. ### Claim 15 (depends on 10) The method of claim 10, wherein the first memory controller port is connected to a first memory redrive device and the second memory controller port is connected to a second memory redrive device, wherein the first memory redrive device is connected to a first memory structure and the second memory redrive device is connected to a second memory structure. ### Claim 16 A method comprising: receiving, in response to a detected error, a retrain request from a memory controller; issuing a first command to refresh a subset of a plurality of memory ranks that have not received a refresh subsequent to the plurality of memory ranks exiting a first self-timed refresh mode; and issuing a second command instructing the plurality of memory ranks to enter a second self-timed refresh mode, wherein the second command is different from the first command. ### Claim 17 (depends on 16) The method of claim 16 further comprising maintaining a refresh observed flag that corresponds to a memory rank of the plurality of memory ranks, wherein the refresh observed flag indicates whether the memory rank has received the refresh subsequent to the plurality of memory ranks exiting the first self-time refresh mode. ### Claim 18 (depends on 17) The method of claim 17, further comprising determining that the subset of the plurality of memory ranks that have not received the refresh subsequent to the memory ranks exiting the first self-timed refresh mode based on the refresh observed flags. ### Claim 19 (depends on 16) The method of claim 16, wherein the retrain request is received via a high speed link connecting the memory controller to a redrive device. ### Claim 20 (depends on 16) The method of claim 16, wherein the plurality of memory ranks include a double data rate type three synchronous dynamic random access memory (DDR3 SDRAM).