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US 8,572,453 B2Granted
Error correcting decoding apparatus for decoding low-density parity-check codes
AssigneeSumitomo Electric Industries, Ltd.
InventorTakashi Maehata
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Abstract
A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.
Claims9
An error correcting decoding apparatus for performing decoding in units of code length N, comprising:
- a decoder;
- and
- a serial-parallel conversion circuit, wherein:
- B1 (B1 is a natural number of at least 2 and less than N) first lines connecting said serial-parallel conversion circuit with said decoder, one input data being transmitted through each first line,
- said serial-parallel conversion circuit converts N input data applied in series to parallel data dividedly over several times,
- parallel number of parallel data generated in each time of conversion in up to B1,
- said serial-parallel conversion circuit provides said parallel data generated in each time of the conversion to said decoder through said B1 first lines, and
- said decoder decodes said N input data, which are provided by said serial-parallel conversion circuit, in parallel.
5 more elements
An error correcting decoding apparatus for performing decoding in units of decode length K, comprising:
- a decoder applying decode processing to input data in parallel to generate K decode data;
- and
- a parallel-serial conversion circuit, wherein:
- B2 (B2 is a natural number of at least 2 and less than K) second lines connecting said decoder with said parallel-serial conversion circuit,
- said parallel-serial conversion circuit receives K decode data from said decoder through said B2 second lines dividedly over several times,
- parallel number of decode data received in each time is up to B2, and
- said parallel-serial conversion circuit converts parallel decode data received in each time to serial data and outputs the serial data to an external source.
4 more elements
Dependencies are inferred from the claim text.