Circuitry for built-in self-test
AssigneeSTMicroelectronics (Grenoble 2) SAS
InventorHervé Le-Gall
Life of this patent
Estimating the term…
Abstract
A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.
Claims32
A method of testing a data connection using at least one test sequence, the method comprising:
- providing a first bit sequence by a first generator;
- duplicating said first bit sequence to generate a second bit sequence identical to the first;
- and
- generating said at least one test sequence based on said first and second bit sequences and transmitting said at least one test sequence over a data connection to be tested.
Circuitry for testing a data connection using at least one test sequence, the circuitry comprising:
- a first generator arranged to generate a first bit sequence;
- and
- signal processing circuitry arranged to duplicate said first bit sequence to generate a second bit sequence identical to the first bit sequence, and to generate said at least one test sequence based on said first and second bit sequences.
A method for testing a data connection, comprising:
- generating, by a first generator, a first bit sequence;
- duplicating the first bit sequence to provide a second bit sequence identical to the first bit sequence;
- generating at least one test sequence including at least portions of the first and second bit sequences;
- and
- transmitting the at least one test sequence over the data connection.
Apparatus for testing a data connection, comprising:
- a first generator configured to generate a first bit sequence;
- and
- a circuit configured to duplicate the first bit sequence to provide a second bit sequence identical to the first bit sequence and to generate at least one test sequence including at least portions of the first and second bit sequences.
Dependencies are inferred from the claim text.