Output circuitry with tri-state buffer and comparator circuitry
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.
Claims3
An integrated circuit comprising:
- A. input pads;
- B. output pads;
- C. core circuitry coupled between the input pads and the output pads;
- and
- D. output circuitry coupled between the core circuitry and the output pads, for each output pad the output circuitry including:
- i. a tri-state buffer having a core input lead connected to a core output lead of the core circuitry, a data output lead connected to an output pad and an enable input lead carrying an enable signal that can place the data output lead of the tri-state buffer in a high impedance state;
- and
- ii. comparator circuitry having a core input lead connected to the core output lead and the core input lead of the tri-state buffer, an encoded response input lead connected to the output pad and the data output lead of the tri-state buffer, and an enable input lead connected to the enable input lead of the tri-state buffer, the comparator circuitry including a compare gate, a pass/fail latch, and a scan cell, the compare gate being connected to the core input lead and the encoded response lead, the pass/fail latch being coupled to the output of the compare gate to store the result of a compare, and the scan cell being coupled to the output of the pass/fail latch and having an scan input lead, a scan output lead and a scan control lead, and the comparator circuitry including a transistor having a gate connected to the output of the pass/fail latch, a terminal connected to ground, and another terminal connected to a fail output lead extending from the comparator circuitry.
Dependencies are inferred from the claim text.