# US 8,572,424 B2 · Semiconductor device to select and output data to a data bus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,424 B2 - Document ID: US8572424B2 - Status: Granted - Kind: B2 - Application number: 11/806,327 - Filed: 2007-05-31 - Published: 2007-10-11 - Granted: 2013-10-29 - Earliest claimed: 2002-04-10 - Assignees: Fujitsu Semiconductor Limited - Applicants: Miki Yanagawa - Inventors: Miki Yanagawa - Web page: https://patentgrep.com/patent/US8572424B2 ## CPC - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G06F 13/4018: {with data-width conversion} - G11C 7/1045: {Read-write mode select circuits} - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/106: {Data output latches} - H03K 5/135: by the use of time reference signals, e.g. clock signals - H03M 9/00: Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract A semiconductor device that can transmit data in wide bus width regardless of the width of an external data bus connected thereto. In a semiconductor device on the data output side, m-bit internal data is divided into n blocks. A data selection circuit selects m/n pieces of data at a time and a data output section outputs these pieces of data to an external data bus of a width of L(=m/n) bits. At this time an output control circuit controls the selection of data by the data selection circuit and a synchronous signal output section outputs a synchronous signal indicative of selected data. In a semiconductor device on the data input side, a data input section accepts data transferred via an external data bus and a data get circuit outputs the data to an internal data bus corresponding to a synchronous signal a synchronous signal input section accepted. By getting data corresponding to all synchronous signals, the data get circuit will get m-bit data. ## Claims ### Claim 1 A semiconductor device which outputs internal data to an external data bus, the device comprising; an internal data bus, a width of which is four times wider than a width of the external data bus; an output control circuit configured to generate a plurality of selection signals in parallel in response to an output start signal; a data selection circuit configured to select a data block from four divided data blocks on the internal data bus according to the selection signals which are supplied in parallel to the data selection circuit; a data output section configured to output the data in the data block selected by the data selection circuit to the external data bus; and a synchronous signal output section configured to output strobe signals to synchronous signal lines in response to the selection signals. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the synchronous signal output section operates in synchronization with a system clock to align strobe signal transitions with the system clock. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the synchronous signal output section operates in synchronization with a first s stem system clock and the data output section operates in synchronization with a second output clock. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the data selection circuit includes a plurality of multiplexers configured to select a datablock from data blocks, wherein each of the plurality of selection signals is supplied to the corresponding multiplexers. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising: an internal data latch circuit configured to latch data inputted from the outside of the semiconductor device. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the data selection circuit includes an internal data latch circuit configured to latch data inputted from the outside of the semiconductor device. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the data output section includes output latch circuits configured to latch-data selected by the data selection circuit in synchronization with a second (output) clock signal. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the data output section includes output buffers configured to output data latched by the output latch circuits to the external data bus. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the synchronous signal output section outputs the strobe signals in synchronization with the data. ### Claim 10 A semiconductor device which outputs internal data to an external data bus of a width narrower than the width of an internal data bus, the device comprising: an output control circuit configured to generate a plurality of selection signals and output the plurality of selection signals in parallel in response to an output start signal; a data selection circuit configured to select a data block from n divided data blocks on the internal data bus having a width of m bits according to the selection signals which are supplied in parallel to the data selection circuit; a data output section configured to output the data in the data block selected by the data selection circuit to the external data bus having a width of m/n bits; and a synchronous signal output section configured to output strobe signals to synchronous signal lines in response to the selection signals. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the synchronous signal output section operates in synchronization with a system clock to align strobe signal transitions with the system clock. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein the synchronous signal output section operates in synchronization with a first system clock and the data output section operates in synchronization with a second output clock. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein the data selection circuit includes a plurality of multiplexers configured to select a data block from data blocks, wherein each of the plurality of selection signals is supplied to the corresponding multiplexer. ### Claim 14 (depends on 10) The semiconductor device according to claim 10, further comprising: an internal data latch circuit configured to latch data inputted from the outside of the semiconductor device. ### Claim 15 (depends on 10) The semiconductor device according to claim 10, wherein the data selection circuit includes an internal data latch circuit configured to latch data inputted from the outside of the semiconductor device. ### Claim 16 (depends on 10) The semiconductor device according to claim 10, wherein the data output section includes output latch circuits configured to latch data selected by the data selection circuit in synchronization with a second output clock signal. ### Claim 17 (depends on 10) The semiconductor device according to claim 10, wherein the data output section includes output buffers configured to output data latched by the output latch circuits to the external data bus. ### Claim 18 (depends on 10) The semiconductor device according to claim 10, wherein the synchronous signal output section outputs the strobe signals in synchronization with the data. ### Claim 19 A semiconductor device which outputs internal data to an external data bus, the device comprising: an internal data bus, a width of which is four times wider than a width of the external data base; an output control circuit configures to generate a plurality of selection signals in parallel in response to an output start signal; a data selection circuit configured to select a data block from four divided data blocks on the internal data bus according to the selection signals which are supplied in parallel to the data selection circuit; a data output section configured to output data in the data block selected by the data selection circuit to the external data bus; and a synchronous signal output section configured to output strobe signals corresponding to the selection signals to synchronous signal lines in synchronized with an output of the data in the data block selected by the data selection circuit based on the selection signals from the data output section. ### Claim 20 A semiconductor device which outputs internal data to an external data bus of a width narrower than the width of an internal data bus, the device comprising: an output control circuit configured to generate a plurality of selection signals and output the plurality of selection signals in parallel in response to an output start signal; a data selection circuit configured to select a data block from n divided data blocks on the internal data bus having a width of m bits according to the selection signals which are supplied in parallel to the data selection circuit; a data output section configured to output the data in the data block selected by the data selection circuit to the external data bus having a width of m/n bits; and a synchronous signal output section configured to output strobe signals corresponding to the selection signals to synchronous signal lines in synchronized with an output of the data in the data block selected by the data selection circuit based on the selection signals from the data output section.