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US 8,572,418 B2Granted
Moving clock gating cell closer to clock source based on enable signal propagation time to clocked storage element
AssigneeQUALCOMM Incorporated
InventorChandrasekhar Singasani
Life of this patent
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Abstract
In a particular embodiment, a method of generating an advanced gating cell clock tree includes determining a timing margin for a path between a clock gating cell and a digital data storage element such as a latch or flip flop. The circuit contains a clock source and when the timing margin for the path meets a predetermined threshold, the clock gating cell is automatically moved closer to the clock source. In a particular embodiment, the timing margin is automatically determined. A clock tree synthesis is performed to insert one or more buffers into the path and create an advanced gating cell clock tree.
Claims30
An apparatus, comprising:
- a semiconductor device comprising:
- a clock signal generator;
- a plurality of digital data storage elements coupled to the clock signal generator by respective paths;
- and
- a respective clock gating cell positioned on each of the paths, wherein a particular clock gating cell is positioned on a particular path at a location based on a signal propagation time to propagate an enable signal to a particular digital data storage element associated with the particular path from the particular clock gating cell.
2 more elements
An apparatus, comprising:
- means for generating a clock signal;
- means for coupling a plurality of digital data storage elements to the clock signal by respective paths;
- and
- means for positioning a particular clock gating cell on a particular path at a location based on a signal propagation time to propagate an enable signal to a particular digital data storage element associated with the particular path from the particular clock gating cell.
1 more element
A method, comprising:
- determining, with a processor, a timing margin for a path between a clock gating cell and a digital data storage element in a circuit comprising a clock source coupled to the digital storage element via the clock gating cell, wherein the timing margin includes a signal propagation time to propagate an enable signal from the clock gating cell to the digital data storage element;
- and
- positioning the clock gating cell at a location on the path based on the signal propagation time.
A method, comprising:
- a first step for determining a timing margin for a path between a clock gating cell and a digital data storage element in a circuit comprising a clock source coupled to the digital storage element via the clock gating cell, wherein the timing margin includes a signal propagation time to propagate an enable signal from the clock gating cell to the digital data storage element;
- and
- a second step for positioning the clock gating cell at a location on the path based on the signal propagation time.
A non-transitory computer readable medium comprising instructions that, when executed by a processor, cause the processor to:
- determine a timing margin for a path between a clock gating cell and a digital data storage element in a circuit comprising a clock source coupled to the digital storage element via the clock gating cell, wherein the timing margin includes a signal propagation time to propagate an enable signal from the clock gating cell to the digital data storage element;
- and
- position the clock gating cell at a location on the path based on the signal propagation time.
A method, comprising:
- receiving design information representing at least one physical property of a semiconductor device, wherein the semiconductor device comprises:
- a clock signal generator;
- a plurality of digital data storage elements coupled to the clock signal generator by respective paths;
- and
- a respective clock gating cell positioned on each of the paths, wherein a particular clock gating cell is positioned on a particular path at a location based on a signal propagation time to propagate an enable signal to a particular digital data storage element associated with the particular path from the particular clock gating cell;
- transforming the design information to comply with a file format;
- and
- generating a data file including the transformed design information.
5 more elements
A method, comprising:
- receiving a data file including design information corresponding to a semiconductor device;
- and
- fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
- a clock signal generator;
- a plurality of digital data storage elements coupled to the dock signal generator by respective paths;
- and
- a respective clock gating cell positioned on each of the paths, wherein a particular clock gating cell is positioned on a particular path at a location based on a signal propagation time to propagate an enable signal to a particular digital data storage element associated with the particular path from the particular clock gating cell.
4 more elements
A method, comprising:
- receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising:
- a clock signal generator;
- a plurality of digital data storage elements coupled to the clock signal generator by respective paths;
- a respective clock gating cell positioned on each of the paths, wherein a particular clock gating cell is positioned on a particular path at a location based on a signal propagation time to propagate an enable signal to a particular digital data storage element associated with the particular path from the particular clock gating cell.
1 more element
A method, comprising:
- receiving a data file including design information including physical positioning information of a packaged semiconductor device on a circuit board;
- and
- manufacturing the circuit board configured to receive the packaged semiconductor device according to the design information, wherein the packaged semiconductor device comprises a semiconductor device comprising:
- a clock signal generator;
- a plurality of digital data storage elements coupled to the clock signal generator by respective paths;
- a respective clock gating cell positioned on each of the paths, wherein a particular clock gating cell is positioned on a particular path at a location based on a signal propagation time to propagate an enable signal to a particular digital data storage element associated with the particular path from the particular clock gating cell.
3 more elements
Dependencies are inferred from the claim text.