US 8,572,356 B2 · Space-efficient mechanism to support additional scouting in a processor using checkpoints

Abstract

Techniques and structures are disclosed for a processor supporting checkpointing to operate effectively in scouting mode while a maximum number of supported checkpoints are active. Operation in scouting mode may include using bypass logic and a set of register storage locations to store and/or forward in-flight instruction results that were calculated during scouting mode. These forwarded results may be used during scouting mode to calculate memory load addresses for yet other in-flight instructions, and the processor may accordingly cause data to be prefetched from these calculated memory load addresses. The set of register storage locations may comprise a working register file or an active portion of a multiported register file.

Claims20

Dependent claims

An apparatus, comprising:

a processor, wherein the processor includes:
an execution pipeline;
and
one or more sets of checkpoint storage locations configured to store state information associated with up to a maximum of N checkpoints that the processor is configured to take in response to detecting corresponding checkpoint conditions, wherein N is at least one;
wherein the processor is configured, subsequent to detecting a checkpoint condition and having the maximum N checkpoints be in use, to execute additional instructions in scouting mode without using the one or more sets of checkpoint storage locations to store results of the additional instructions, including forwarding values to the execution pipeline to be used as instruction operands during scouting mode.

2 more elements

A method, comprising:

a processor detecting a checkpoint condition during execution of an instruction stream, wherein subsequent to the checkpoint condition being detected, N sets of N maximum available checkpoint storage locations are being used to store state information associated with N active checkpoints taken by the processor, wherein N is at least one;
and
in response to said detecting the checkpoint condition, the processor executing additional instructions of the instruction stream in scouting mode without storing results of the additional instructions in the N maximum available checkpoint storage locations, and including forwarding values to an execution pipeline of the processor be used as instruction operands during scouting mode.

An apparatus, comprising:

one or more sets of checkpoint storage locations configured to store information associated with up to a maximum number of N checkpoints taken by the apparatus, wherein N is at least one;
an architected register file configured to store results of committed instructions;
and
a set of register storage locations configured to store results of in-flight instructions;
wherein the apparatus is configured, in response to the apparatus detecting a checkpoint condition in association with the one or more sets of checkpoint storage locations being used to store the maximum number of N active checkpoints, to operate in scouting mode, including:
storing, in the architectural register file, information specifying a state of the processor, wherein the stored state is usable to resume execution at the detected checkpoint condition;
and
forwarding results in the set of register storage locations as operands for instructions that occur subsequent in program order to the checkpoint condition, wherein results of the instructions that occur subsequent in program order to the checkpoint condition are not stored in the one or more sets of checkpoint storage locations.

5 more elements

Dependencies are inferred from the claim text.

Space-efficient mechanism to support additional scouting in a processor using checkpoints

Life of this patent

Space-efficient mechanism to support additional scouting in a processor using checkpoints

Life of this patent

Abstract

Claims20