# US 8,572,355 B2 · Support for non-local returns in parallel thread SIMD engine > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,355 B2 - Document ID: US8572355B2 - Status: Granted - Kind: B2 - Application number: 12/881,065 - Filed: 2010-09-13 - Published: 2011-03-31 - Granted: 2013-10-29 - Earliest claimed: 2009-09-28 - Assignees: NVIDIA Corporation - Applicants: Guillermo Juan Rozas; Brett W. Coon - Inventors: Guillermo Juan Rozas; Brett W. Coon - Web page: https://patentgrep.com/patent/US8572355B2 ## CPC - G06F 9/30058: {Conditional branch instructions} - G06F 9/323: {for indirect branch instructions} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack. ## Claims ### Claim 1 A method for executing a non-local return instruction in a parallel thread processor, the method comprising: receiving, within a thread group including a plurality of active threads, a first long jump instruction; in response to the first long jump instruction, popping a first token from an execution stack; determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, wherein the first long jump token specifies an address of a second instruction; and for each active thread in the thread group, when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack. ### Claim 2 (depends on 1) The method of claim 1, further comprising the step of, in response to the first push instruction, incrementing a long jump counter associated with the thread group. ### Claim 3 (depends on 2) The method of claim 2, further comprising the step of, in response to the first push instruction, storing a first value of the long jump counter that corresponds to the incremented long jump counter. ### Claim 4 (depends on 3) The method of claim 3, wherein the step of determining whether the first token is the first long jump token comprises comparing the first value of the long jump counter with a current value of the long jump counter. ### Claim 5 (depends on 4) The method of claim 4, wherein the first token is the first long jump token when the first value of the long jump counter corresponds to the current value of the long jump counter. ### Claim 6 (depends on 4) The method of claim 4, wherein the first token is not the first long jump token when the first value of the long jump counter does not correspond to the current value of the long jump counter. ### Claim 7 (depends on 6) The method of claim 6, further comprising the step of decrementing the long jump counter associated with the thread group when the first token is not the first long jump token. ### Claim 8 (depends on 7) The method of claim 7, further comprising the step of, after decrementing the long jump counter, popping a second token from the execution stack. ### Claim 9 (depends on 8) The method of claim 8, further comprising the step of determining whether the second token is the first long jump token. ### Claim 10 (depends on 1) The method of claim 1, wherein the first push instruction and the first long jump instruction are inserted into a shader program by a compiler, wherein the shader program is executed by the thread group. ### Claim 11 A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to execute a non-local return instruction in a parallel thread processor, by performing the steps of: receiving, within a thread group including a plurality of active threads, a first long jump instruction; in response to the first long jump instruction, popping a first token from an execution stack; determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, wherein the first long jump token specifies an address of a second instruction; and for each active thread in the thread group, when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack. ### Claim 12 (depends on 11) The non-transitory computer-readable storage medium of claim 11, further comprising the step of, in response to the first push instruction, incrementing a long jump counter associated with the thread group. ### Claim 13 (depends on 12) The non-transitory computer-readable storage medium of claim 12, further comprising the step of, in response to the first push instruction, storing a first value of the long jump counter that corresponds to the incremented long jump counter. ### Claim 14 (depends on 13) The non-transitory computer-readable storage medium of claim 13, wherein the step of determining whether the first token is the first long jump token comprises comparing the first value of the long jump counter with a current value of the long jump counter. ### Claim 15 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the first token is the first long jump token when the first value of the long jump counter corresponds to the current value of the long jump counter. ### Claim 16 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the first token is not the first long jump token when the first value of the long jump counter does not correspond to the current value of the long jump counter. ### Claim 17 (depends on 16) The non-transitory computer-readable storage medium of claim 16, further comprising the step of decrementing the long jump counter associated with the thread group when the first token is not the first long jump token. ### Claim 18 (depends on 17) The non-transitory computer-readable storage medium of claim 17, further comprising the step of, after decrementing the long jump counter, popping a second token from the execution stack. ### Claim 19 (depends on 11) The non-transitory computer-readable storage medium of claim 11, wherein the first push instruction and the first long jump instruction are inserted into a shader program by a compiler, wherein the shader program is executed by the thread group. ### Claim 20 A computing device, comprising: a memory; and a processor configured to: receive, within a thread group including a plurality of active threads, a first long jump instruction; in response to the first long jump instruction, pop a first token from an execution stack; determine whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, wherein the first long jump token specifies an address of a second instruction; and for each active thread in the thread group, when the first token is the first long jump token, jump to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disable the active thread until the first long jump token is popped from the execution stack.