# US 8,572,354 B2 · Programmable logic unit and method for translating and processing instructions using interpretation registers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,572,354 B2 - Document ID: US8572354B2 - Status: Granted - Kind: B2 - Application number: 11/536,483 - Filed: 2006-09-28 - Published: 2008-04-03 - Granted: 2013-10-29 - Earliest claimed: 2006-09-28 - Assignees: 3Dlabs Inc., Ltd. - Applicants: Jonathan Bloomfield; John Robson; Nick Murphy - Inventors: Jonathan Bloomfield; John Robson; Nick Murphy - Web page: https://patentgrep.com/patent/US8572354B2 ## CPC - G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields} - G06F 9/3013: {according to data content, e.g. floating-point registers, address registers} - G06F 9/30178: {of compressed or encrypted instructions} - G06F 9/30185: {according to one or more bits in the instruction, e.g. prefix, sub-opcode} - G06F 9/30192: {according to data descriptor, e.g. dynamic data typing} - G06F 9/3822: {Parallel decoding, e.g. parallel decode units} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An architecture for microprocessors, in which instructions include a type identifier, selects one of several interpretation registers. The interpretation registers hold information for interpreting the opcode of each instruction, so that a stream of compressed instructions (with type identifiers) can be translated into a stream of expanded instructions. Preferably the type identifiers also distinguish sequencer instructions from processing-element instructions, and can even distinguish among different types of sequencer instructions (as well as among different types of processing-element instructions). ## Claims ### Claim 1 A programmable logic unit, comprising: one or more programmable processing elements; and a sequencer which decodes instructions in an instruction stream using indirect reference to multiple interpretation registers, as specified by a Type Identifier (ID) value and an opcode value within said instructions, and sends commands derived from the instruction stream to said one or more processing elements; wherein said interpretation registers include identifiers defining respective mappings of opcodes to one of a plurality of instruction groups, and said commands being at least partly determined by said mappings; and wherein said interpretation registers include operand control information that comprises a vector length and a stride between vector elements. ### Claim 2 (depends on 1) The unit of claim 1, wherein said instruction stream includes both processing instructions and sequencing instructions. ### Claim 3 (depends on 1) The unit of claim 1, wherein said instruction stream includes both processing instructions and sequencing instructions, and wherein both said processing instructions and said sequencing instructions include said Type ID value, and wherein said Type ID value also indicates whether each instruction is a processing instruction or a sequencing instruction. ### Claim 4 (depends on 1) The unit of claim 1, wherein said instruction stream includes both processing instructions and sequencing instructions, and said sequencing instructions include commands for changing the values in at least some ones of said interpretation registers. ### Claim 5 (depends on 1) The unit of claim 1, wherein said commands are expanded by at least one sequencer; and wherein said instruction stream includes both processing instructions and sequencing instructions; and wherein said sequencing instructions include set-up commands which are executed by the at least one sequencer and not by said one or more processing elements, said set-up commands including commands for changing the values in an interpretation register. ### Claim 6 (depends on 1) The unit of claim 1, wherein said commands are expanded by at least one sequencer; and wherein the at least one sequencer broadcasts a single instruction stream to multiple processing elements in a single instruction, multiple data (SIMD) configuration. ### Claim 7 (depends on 1) The unit of claim 1, wherein each single one of said instructions specifies only a single opcode. ### Claim 8 (depends on 1) The unit of claim 1, wherein each of said instructions of said instruction stream includes an index number which selects a respective portion of said interpretation registers, and wherein said sequencer expands said instructions by using said respective portion of said interpretation registers. ### Claim 9 A method of executing a series of instructions, comprising the steps of: a) interpreting each of the instructions with reference to a respective one of multiple interpretation registers specified in a Type Identifier (ID) field of said instructions, the interpretation registers including identifiers that define respective mappings of opcodes to instruction groups and operand control information including vector length and stride between vector elements, wherein commands associated with the opcodes are at least partly determined by said mappings, and wherein said operand control information comprises control of an operand data type; and b) executing said instructions. ### Claim 10 (depends on 9) The method of claim 9, wherein said series of instructions includes both processing instructions and sequencing instructions. ### Claim 11 (depends on 9) The method of claim 9, wherein said series of instructions includes both processing instructions and sequencing instructions, and wherein said Type ID field also indicates whether each instruction is a processing instruction or a sequencing instruction. ### Claim 12 (depends on 9) The method of claim 9, wherein said series of instructions includes both processing instructions and sequencing instructions, and said sequencing instructions include commands for changing the values in at least one interpretation register. ### Claim 13 (depends on 9) The method of claim 9, wherein at least one instruction of said series of instructions is expanded by at least one sequencer; wherein said series of instructions includes both processing instructions and sequencing instructions; and wherein said sequencing instructions include set-up commands which are executed by a sequencer and not by processing elements, said set-up commands including commands for changing the bit values in the interpretation registers. ### Claim 14 (depends on 9) The method of claim 9, wherein said instructions are expanded by at least one sequencer; and wherein said at least one sequencer broadcasts a single instruction stream to multiple processing elements in a single instruction, multiple data (SIMD) configuration. ### Claim 15 (depends on 9) The method of claim 9, wherein each single processing instruction specifies only a single opcode. ### Claim 16 (depends on 9) The method of claim 9, wherein each of said instructions includes an index number which selects a respective particular portion of a respective interpretation register, and wherein a sequencer expands said instructions by using said respective particular portion of said respective interpretation register. ### Claim 17 A method for executing a series of instructions, comprising the steps of: a) interpreting each of the instructions using an indirect reference to a respective one of multiple interpretation registers which is specified in a Type Identifier (ID) field of said instructions, the interpretation registers including operand control information including vector length and stride between vector elements; wherein said Type ID field distinguishes between sequencer instructions and processing-element instructions, and also distinguishes among multiple different formats for processing-element instructions; wherein the respective interpretation register includes an identifier that selects respective mappings of opcodes to instruction groups, and commands associated with the opcodes are at least partly determined by said mappings, and b) executing said instructions. ### Claim 18 (depends on 17) The method of claim 17, further comprising: changing the values in at least some ones of said interpretation registers in response to commands included within sequencer instructions. ### Claim 19 (depends on 17) The method of claim 17, further comprising: expanding said instructions using at least one sequencer; and wherein said sequencer instructions include set-up commands which are executed only by a sequencer. ### Claim 20 (depends on 17) The method of claim 17, wherein said sequencer instructions include commands for changing the bit values in the respective interpretation register.